sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

138

watch_address_high = upper_32_bits(watch_address) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

168

upper_32_bits(data64));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

104

upper_32_bits(data64));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

341

upper_32_bits(guessed_wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

345

upper_32_bits((uintptr_t)wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

476

watch_address_high = upper_32_bits(watch_address) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1059

upper_32_bits(tba_addr >> 8) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1068

upper_32_bits(tma_addr >> 8));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

266

upper_32_bits(guessed_wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

270

upper_32_bits((uint64_t)wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

418

upper_32_bits(data64));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

485

high = upper_32_bits(queue_address >> 8);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

902

watch_address_high = upper_32_bits(watch_address) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

252

upper_32_bits(guessed_wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

256

upper_32_bits((uint64_t)wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

404

upper_32_bits(data64));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

471

high = upper_32_bits(queue_address >> 8);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

644

upper_32_bits(tba_addr >> 8) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

653

upper_32_bits(tma_addr >> 8));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

237

upper_32_bits(guessed_wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

241

upper_32_bits((uint64_t)wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

389

upper_32_bits(data64));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

460

high = upper_32_bits(queue_address >> 8);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

755

watch_address_high = upper_32_bits(watch_address) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

330

watch_address_high = upper_32_bits(watch_address) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

332

high = upper_32_bits(queue_address >> 8);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

364

high = upper_32_bits(queue_address >> 8);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1114

upper_32_bits(tba_addr >> 8));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1122

upper_32_bits(tma_addr >> 8));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

280

upper_32_bits(guessed_wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

284

upper_32_bits((uintptr_t)wptr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

429

upper_32_bits(data64));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

496

high = upper_32_bits(queue_address >> 8);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

833

watch_address_high = upper_32_bits(watch_address) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

325

reg_data.status_hi = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

327

reg_data.addr_hi = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

329

reg_data.ipid_hi = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

331

reg_data.synd_hi = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

419

reg_data[CPER_ACA_REG_CTL_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CTL]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

421

reg_data[CPER_ACA_REG_STATUS_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

423

reg_data[CPER_ACA_REG_ADDR_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

425

reg_data[CPER_ACA_REG_MISC0_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_MISC0]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

427

reg_data[CPER_ACA_REG_CONFIG_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CONFIG]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

429

reg_data[CPER_ACA_REG_IPID_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

431

reg_data[CPER_ACA_REG_SYND_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

543

if (upper_32_bits(*pos))

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

607

if (upper_32_bits(*pos))

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

939

config[no_regs++] = upper_32_bits(adev->cg_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1167

cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1326

cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1332

upper_32_bits(context->mem_context.shared_mc_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2911

cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3470

write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3472

write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

811

cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

815

cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

823

cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

936

amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

1075

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

1095

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

498

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

685

amdgpu_ib_set_value(ib, hi, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1021

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

954

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

537

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

540

amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

554

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

555

amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

580

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

626

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

752

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

765

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

769

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

799

amdgpu_ring_write(ring, upper_32_bits(wb_addr));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

841

ib.ptr[2] = upper_32_bits(wb_addr);

sys/dev/pci/drm/amd/amdgpu/atom.c

717

ctx->ctx->divmul[1] = upper_32_bits(val64);

sys/dev/pci/drm/amd/amdgpu/atom.c

839

ctx->ctx->divmul[1] = upper_32_bits(val64);

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

137

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1297

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1299

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1319

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

235

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

285

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

293

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

294

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

470

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

623

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

678

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

728

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

730

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

753

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

757

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

781

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

783

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

785

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

833

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

139

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2019

upper_32_bits(fb_location));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2021

upper_32_bits(fb_location));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2306

upper_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

251

upper_32_bits(crtc_base));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2037

upper_32_bits(fb_location));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2039

upper_32_bits(fb_location));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

215

upper_32_bits(crtc_base));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2277

upper_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1949

upper_32_bits(fb_location));

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1951

upper_32_bits(fb_location));

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

199

upper_32_bits(crtc_base));

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2225

upper_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3719

amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3721

amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3761

amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3763

amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3784

amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3809

amdgpu_ring_write(kiq_ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3811

amdgpu_ring_write(kiq_ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4100

ib.ptr[3] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5861

WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5913

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5950

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5987

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6024

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6166

upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6243

upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6320

upper_32_bits(adev->gfx.me.me_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6529

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6534

WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6541

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6548

WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6568

WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6572

WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6578

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6585

WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6696

upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6776

mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6801

mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6807

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6812

mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6923

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6959

mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6969

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6991

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6996

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8577

upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8674

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8709

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8740

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8742

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8753

upper_32_bits(addr), seq, 0xffffffff, 4);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8794

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8855

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8932

amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8959

de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8968

amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9000

amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9547

lower_32_bits(addr), upper_32_bits(addr),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1512

WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2526

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2570

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2614

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2632

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2710

upper_32_bits(addr2));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2754

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2833

upper_32_bits(addr2));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2891

upper_32_bits(addr2));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2901

upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3243

upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3321

upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3461

upper_32_bits(adev->gfx.me.me_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3540

upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

360

amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

362

amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3740

WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3745

WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3752

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3759

WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3779

WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3783

WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3789

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3796

WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3985

upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3995

upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

405

amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

407

amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4100

mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4125

mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4131

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4136

mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4172

mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4174

mqd->gds_bkup_base_hi = upper_32_bits(prop->gds_bkup_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4176

mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4178

mqd->fence_address_hi = upper_32_bits(prop->fence_address);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4245

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4281

mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4291

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4314

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4319

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

434

amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4361

mqd->fence_address_hi = upper_32_bits(prop->fence_address);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

459

amdgpu_ring_write(kiq_ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

461

amdgpu_ring_write(kiq_ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5794

upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5889

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5924

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5955

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5957

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5968

upper_32_bits(addr), seq, 0xffffffff, 4);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6015

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6056

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6120

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6126

amdgpu_ring_write(ring, upper_32_bits(shadow_va));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6128

amdgpu_ring_write(ring, upper_32_bits(gds_va));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6130

amdgpu_ring_write(ring, upper_32_bits(csa_va));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6224

de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6233

amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6265

amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

633

ib.ptr[3] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1320

WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2407

upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2458

upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2551

upper_32_bits(adev->gfx.me.me_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2603

upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2736

WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2741

WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2748

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2755

WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2882

upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2888

upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2977

mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

299

amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3005

mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3011

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3016

mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3052

mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3054

mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3056

mqd->fence_address_hi = upper_32_bits(prop->fence_address);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3123

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3159

mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3169

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3191

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3196

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3238

mqd->fence_address_hi = upper_32_bits(prop->fence_address);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

344

amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

346

amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

373

amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

397

amdgpu_ring_write(kiq_ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

399

amdgpu_ring_write(kiq_ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4349

upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4433

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4452

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4481

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4483

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4494

upper_32_bits(addr), seq, 0xffffffff, 4);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4535

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4576

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4649

amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

526

ib.ptr[3] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1846

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1850

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1880

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2105

WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2191

WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2210

WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2297

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2399

dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2137

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2140

amdgpu_ring_write(ring, upper_32_bits(seq - 1));

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2150

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2153

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2182

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2184

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2231

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2265

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2574

WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2584

WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2784

WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2850

mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2859

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2886

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2892

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3117

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3804

WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1538

ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1564

ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1590

ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4260

WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4264

WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4270

WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4334

amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4355

amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4357

amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4415

mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4419

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4438

mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4448

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4469

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4474

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6071

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6105

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6126

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6129

amdgpu_ring_write(ring, upper_32_bits(seq - 1));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6141

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6144

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6159

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6221

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6223

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6237

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6297

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6319

amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7144

amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7161

de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7166

de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7177

amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

894

ib.ptr[3] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1026

amdgpu_ring_write(kiq_ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1028

amdgpu_ring_write(kiq_ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1250

ib.ptr[3] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3414

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3419

WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3423

WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3430

WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3503

upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3568

upper_32_bits(ring->mqd_gpu_addr

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3573

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3610

mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3620

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3641

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3646

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4221

amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4701

ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4729

ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4757

ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5374

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5443

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5539

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5578

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5580

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5591

lower_32_bits(addr), upper_32_bits(addr),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5651

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5691

amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5779

de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5789

amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5848

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5870

amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

944

upper_32_bits(queue_mask)); /* queue mask hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

946

amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

976

amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

978

amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

393

ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

400

ib->ptr[ib->length_dw++] = upper_32_bits(wb_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1780

upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1844

upper_32_bits(ring->mqd_gpu_addr

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1849

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1889

mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1899

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

192

upper_32_bits(queue_mask)); /* queue mask hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1920

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1925

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

194

amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

225

amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

227

amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

248

amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

274

amdgpu_ring_write(kiq_ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

276

amdgpu_ring_write(kiq_ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2880

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2912

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2914

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2925

lower_32_bits(addr), upper_32_bits(addr),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2978

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3007

amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

477

ib.ptr[3] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

135

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

336

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

138

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

341

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

306

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

51

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

395

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

60

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

131

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

326

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

134

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

338

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

130

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

333

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

133

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

338

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

402

upper_32_bits(pd_addr));

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

394

upper_32_bits(pd_addr));

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

430

upper_32_bits(pd_addr));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1013

upper_32_bits(pd_addr));

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

139

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

298

WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

270

WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

270

WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

244

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

268

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

322

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

334

amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

540

WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

72

val = upper_32_bits(ring->gpu_addr);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

367

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

522

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

583

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

595

amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

371

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

387

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

423

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

479

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

506

WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

294

MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

320

WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

595

reg_offset, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

801

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

856

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

868

amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

468

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

553

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

391

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

468

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

432

reg_offset, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

492

MMSCH_V5_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

518

WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

48

WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr));

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

51

WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr));

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

83

WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr));

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

48

WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr));

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

51

WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr));

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

83

WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1040

upper_32_bits(ucode_addr));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1046

upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1055

upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1128

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1139

mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1149

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1155

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1160

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

953

upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

977

upper_32_bits(ucode_addr));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1100

upper_32_bits(adev->mes.event_log_gpu_addr +

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1119

upper_32_bits(ucode_addr));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1169

upper_32_bits(ucode_addr));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1208

upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1217

upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1288

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1299

mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1309

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1315

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1320

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

243

upper_32_bits(pt_base >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

330

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

65

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

340

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

63

hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

439

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

73

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

201

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

410

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

131

hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

326

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

148

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

364

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

157

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

358

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

141

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

356

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

248

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

451

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

479

upper_32_bits(pt_base >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

140

upper_32_bits(page_table_base));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

357

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

389

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

70

upper_32_bits(value));

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

294

WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

179

upper_32_bits(adev->doorbell.base));

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

178

upper_32_bits(adev->doorbell.base));

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

174

upper_32_bits(adev->doorbell.base));

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

125

upper_32_bits(adev->doorbell.base));

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

167

upper_32_bits(adev->doorbell.base));

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

180

upper_32_bits(adev->doorbell.base));

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

227

upper_32_bits(adev->doorbell.base));

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

137

upper_32_bits(adev->doorbell.base));

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

257

upper_32_bits(adev->doorbell.base));

sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c

82

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

333

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

362

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c

110

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c

81

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

154

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

424

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

453

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

786

WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

821

WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

242

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

271

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

289

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

318

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

657

WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

208

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

229

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1192

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1194

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1214

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

261

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

314

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

322

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

323

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

445

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

555

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

610

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

664

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

666

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

689

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

693

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

717

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

719

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

721

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

769

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1042

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1634

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1636

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1656

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

437

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

490

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

498

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

499

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

686

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

712

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

829

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

884

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

937

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

939

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

962

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

966

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

990

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

992

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

994

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1109

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1145

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1194

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1231

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1487

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1542

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1597

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1599

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1623

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1627

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1652

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1654

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1656

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1701

upper_32_bits(addr) & 0xffffffff,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2572

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2574

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2594

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

712

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

725

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

729

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

780

upper_32_bits(wptr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

821

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

895

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

905

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

906

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1083

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1138

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1193

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1195

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1219

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1223

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1248

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1250

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1252

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1297

upper_32_bits(addr) & 0xffffffff,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2273

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2275

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2295

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

279

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

292

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

296

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

347

upper_32_bits(wptr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

388

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

463

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

473

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

474

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

704

upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

731

WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

733

WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

762

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

819

WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

821

WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

831

upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

869

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1042

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1106

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1165

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1167

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1191

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1195

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1220

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1222

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1224

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1273

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

2022

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

2024

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

2044

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

310

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

383

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

397

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

403

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

452

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

455

amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

533

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

544

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

545

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

718

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

720

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

732

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

743

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

764

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

973

m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

980

m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

984

m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1005

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1064

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1066

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1090

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1094

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1119

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1121

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1123

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1173

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1203

upper_32_bits(pd_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

150

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

2026

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

2028

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

2048

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

223

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

238

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

247

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

251

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

300

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

303

amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

383

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

394

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

395

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

567

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

569

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

582

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

593

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

610

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

873

m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

880

m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

884

m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

942

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1011

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1070

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1072

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1096

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1100

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1125

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1127

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1129

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1177

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1206

upper_32_bits(pd_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

151

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1840

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1842

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1862

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

217

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

231

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

237

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

286

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

289

amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

365

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

376

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

377

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

511

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

513

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

525

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

529

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

548

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

869

m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

873

m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

877

m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

895

m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

898

m->sdmax_rlcx_f32_dbg1 = upper_32_bits(prop->fence_address);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

948

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1028

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1089

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1091

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1116

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1120

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1145

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1147

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1149

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1198

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

151

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1783

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1785

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1814

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

219

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

233

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

241

upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

290

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

293

amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

369

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

380

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

381

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

503

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

505

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

517

upper_32_bits(wptr_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

521

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

544

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

725

upper_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

889

m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

893

m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

897

m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

912

m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

915

m->sdmax_rlcx_mcu_dbg1 = upper_32_bits(prop->fence_address);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

965

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/amd/amdgpu/si_dma.c

115

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));

sys/dev/pci/drm/amd/amdgpu/si_dma.c

122

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));

sys/dev/pci/drm/amd/amdgpu/si_dma.c

123

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/pci/drm/amd/amdgpu/si_dma.c

170

WREG32(mmDMA_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

231

amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

284

ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

332

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

333

ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

355

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

358

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

396

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

398

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

400

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

438

amdgpu_ring_write(ring, (0xff << 16) | upper_32_bits(addr)); /* retry, addr_hi */

sys/dev/pci/drm/amd/amdgpu/si_dma.c

790

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

791

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

813

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

91

amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));

sys/dev/pci/drm/amd/amdgpu/si_ih.c

86

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

139

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

104

WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_HI, upper_32_bits(data));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

109

WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_HI, upper_32_bits(data));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

116

upper_32_bits(adev->umsch_mm.data_start_addr));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

125

WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_HI, upper_32_bits(data));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

148

WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, upper_32_bits(umsch->log_gpu_addr));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

229

WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

92

upper_32_bits(adev->umsch_mm.irq_start_addr >> 2));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

97

upper_32_bits(adev->umsch_mm.uc_start_addr >> 2));

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

120

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

420

WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

383

WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

487

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

289

upper_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

434

WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

440

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

502

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

566

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1037

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1062

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1100

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1128

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

233

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

298

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

615

upper_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

851

WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

857

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

872

WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

879

WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

935

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

964

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1099

(upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1105

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1121

WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1128

WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1196

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1230

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1338

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1364

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

241

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

305

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

698

upper_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

709

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

716

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

745

WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

840

upper_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

852

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

859

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

926

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

247

WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

254

WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

284

WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

291

WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

298

WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

869

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

892

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

165

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

237

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

346

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

354

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

362

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

720

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

731

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

34

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

52

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1006

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1013

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1146

(upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1152

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1335

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1342

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1401

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1567

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1610

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1737

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1767

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

372

upper_32_bits(adev->vcn.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

384

upper_32_bits(adev->vcn.inst->gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

392

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

443

upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

455

upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

466

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

982

(upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

988

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1144

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1159

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1168

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1330

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1340

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1548

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1588

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1729

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1759

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1906

WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2009

upper_32_bits(adev->vcn.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2027

upper_32_bits(adev->vcn.inst->gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2043

upper_32_bits(adev->vcn.inst->gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2060

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2075

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

402

upper_32_bits(adev->vcn.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

414

upper_32_bits(adev->vcn.inst->gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

422

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

430

upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

471

upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

492

upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

512

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

524

upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

971

(upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

977

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1132

(upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1138

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1316

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1331

WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1340

WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1367

WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1460

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1477

upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1492

upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1509

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1523

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1699

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1709

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

617

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

628

upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

636

upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

644

upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

684

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

705

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

725

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

737

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1157

(upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1163

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1344

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1363

WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1372

WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1454

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1471

upper_32_bits(cache_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1486

upper_32_bits(cache_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1503

upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1517

upper_32_bits(rb_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1550

WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1757

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1767

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

539

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

550

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

558

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

566

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

606

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

627

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

647

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

659

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1097

WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1287

WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1409

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1426

upper_32_bits(cache_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1441

upper_32_bits(cache_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1465

rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1470

rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1477

rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1486

upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1512

WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

469

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

479

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

487

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

495

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

545

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

566

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

586

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

598

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1061

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1076

regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1089

regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1106

rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1115

upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1133

WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1325

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

480

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

491

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

501

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

513

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

567

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

588

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

609

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

622

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

958

upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1010

WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1200

WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

420

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

430

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

438

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

446

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

499

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

520

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

542

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

555

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

384

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

394

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

402

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

410

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

461

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

482

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

502

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

514

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

767

WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

928

WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1098

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

443

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

454

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

462

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

470

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

523

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

544

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

565

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

578

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

753

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

853

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

868

regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

881

regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

898

rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

907

upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

925

WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

238

WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

274

WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

234

upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

246

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1816

sub_type_hdr->length_high = upper_32_bits(mem_in_bytes);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2002

sub_type_hdr->length_high = upper_32_bits(size);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

117

m->cp_mqd_base_addr_hi = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

193

m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

195

m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

237

m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

239

m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

353

m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

355

m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

115

m->cp_mqd_base_addr_hi = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

137

upper_32_bits(q->ctx_save_restore_area_address);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

179

m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

182

m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

184

m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

206

upper_32_bits(q->eop_ring_buffer_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

377

m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

379

m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

162

m->cp_mqd_base_addr_hi = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

191

upper_32_bits(q->ctx_save_restore_area_address);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

232

m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

235

m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

237

m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

259

upper_32_bits(q->eop_ring_buffer_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

436

m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

438

m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

440

m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

129

m->cp_mqd_base_addr_hi = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

154

upper_32_bits(q->ctx_save_restore_area_address);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

195

m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

198

m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

200

m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

222

upper_32_bits(q->eop_ring_buffer_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

337

m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

339

m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

341

m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

192

m->cp_mqd_base_addr_hi = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

218

upper_32_bits(q->ctx_save_restore_area_address);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

256

m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

259

m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

261

m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

290

upper_32_bits(q->eop_ring_buffer_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

507

m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

509

m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

710

upper_32_bits(xcc_ctx_save_restore_area_address);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

117

m->cp_mqd_base_addr_hi = upper_32_bits(addr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

131

m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

133

m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

144

upper_32_bits(q->ctx_save_restore_area_address);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

185

m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

188

m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

190

m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

217

upper_32_bits(q->eop_ring_buffer_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

371

m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

373

m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

132

packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

134

packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

138

packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

143

upper_32_bits(vm_page_table_base_addr);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

186

packet->ib_base_hi = upper_32_bits(ib);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

213

packet->gws_mask_hi = upper_32_bits(res->gws_mask);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

216

packet->queue_mask_hi = upper_32_bits(res->queue_mask);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

292

upper_32_bits(q->gart_mqd_addr);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

298

upper_32_bits((uint64_t)q->properties.write_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

463

packet->addr_hi = upper_32_bits((uint64_t)fence_address);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

465

packet->data_hi = upper_32_bits((uint64_t)fence_value);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

71

packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

75

packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

79

packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

84

upper_32_bits(vm_page_table_base_addr);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

110

packet->bitfields3.ib_base_hi = upper_32_bits(ib);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

135

packet->gws_mask_hi = upper_32_bits(res->gws_mask);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

138

packet->queue_mask_hi = upper_32_bits(res->queue_mask);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

190

upper_32_bits(q->gart_mqd_addr);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

196

upper_32_bits((uint64_t)q->properties.write_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

264

packet->addr_hi = upper_32_bits((uint64_t)fence_address);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

266

packet->data_hi = upper_32_bits((uint64_t)fence_value);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

294

packet->address_hi = upper_32_bits(gpu_addr);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

71

packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1112

buf[6] = upper_32_bits(local_mem_size);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1517

page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1521

page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1525

page_table_base.high_part = upper_32_bits(pt_base);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9610

attributes.address.high_part = upper_32_bits(address);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1378

attributes.address.high_part = upper_32_bits(address);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

351

address->grph.meta_addr.high_part = upper_32_bits(dcc_address);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

871

address->grph.addr.high_part = upper_32_bits(addr);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

896

upper_32_bits(luma_addr);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

900

upper_32_bits(chroma_addr);

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

211

upper_32_bits((unsigned long)cpu_ptr),

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

213

upper_32_bits(gpu_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

131

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

171

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

268

entry->image_addr_high = upper_32_bits(info.mc_addr);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

307

upper_32_bits(smu_data->smu_buffer.mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

379

upper_32_bits(smu_data->header_buffer.mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

210

reg_data = upper_32_bits(info.mc_addr) &

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

350

task->addr.high = upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

387

task->addr.high = upper_32_bits(smu8_smu->driver_buffer[i].mc_addr);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

615

upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

645

upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

682

upper_32_bits(smu8_smu->toc_buffer.mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

168

upper_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

52

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

97

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

105

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

202

upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

55

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

180

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

230

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

263

upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

293

upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

384

upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

404

upper_32_bits(priv->smu_tables.entry[TABLE_PPTABLE].mc_addr),

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2892

upper_32_bits(dummy_read_table->mc_address),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

639

address_high = (uint32_t)upper_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

656

address_high = (uint32_t)upper_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

695

upper_32_bits(driver_table->mc_address),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

715

upper_32_bits(tool_table->mc_address),

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

276

upper_32_bits(driver_table->mc_address),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

700

address_high = (uint32_t)upper_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

727

upper_32_bits(driver_table->mc_address),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

747

upper_32_bits(tool_table->mc_address),

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

685

address_high = (uint32_t)upper_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

712

upper_32_bits(driver_table->mc_address),

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

732

upper_32_bits(tool_table->mc_address),

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

758

upper_32_bits(feature_mask),

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

769

upper_32_bits(feature_mask),

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

820

upper_32_bits(feature_mask), lower_32_bits(feature_mask));

sys/dev/pci/drm/i915/display/intel_dsb.c

448

upper_32_bits(window));

sys/dev/pci/drm/i915/display/intel_dsb.c

608

upper_32_bits(head_tail));

sys/dev/pci/drm/i915/display/intel_vrr.c

496

upper_32_bits(crtc_state->cmrr.cmrr_m));

sys/dev/pci/drm/i915/display/intel_vrr.c

500

upper_32_bits(crtc_state->cmrr.cmrr_n));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1571

upper_32_bits(plane_state->ccval));

sys/dev/pci/drm/i915/gem/i915_gem_context.c

386

if (upper_32_bits(args->value))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

196

*cs++ = upper_32_bits(i915_vma_offset(dst->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

200

*cs++ = upper_32_bits(i915_vma_offset(src->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

243

*cs++ = upper_32_bits(i915_vma_offset(dst->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

248

*cs++ = upper_32_bits(i915_vma_offset(src->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

225

*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1504

upper_32_bits(offset), lower_32_bits(offset));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1533

*cmd++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1640

*cmd++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1873

upper_32_bits(offset),

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

928

*cmd++ = upper_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

72

*cmd++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/agp_intel_gtt.c

106

upper_32_bits(addr));

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

508

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

565

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

590

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

108

vgtif_reg(pdp[0].hi), upper_32_bits(daddr));

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

122

upper_32_bits(daddr));

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

32

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2127

upper_32_bits(addr), lower_32_bits(addr));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2130

upper_32_bits(addr), lower_32_bits(addr));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2138

upper_32_bits(addr), lower_32_bits(addr));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2234

vma_res ? upper_32_bits(vma_res->start) : ~0u,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1731

XEHP_CSB_CTX_VALID(upper_32_bits(csb)), /* cxt away */

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1732

upper_32_bits(csb) & XEHP_CTX_STATUS_SWITCHED_TO_NEW_QUEUE,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1739

GEN12_CSB_CTX_VALID(upper_32_bits(csb)), /* cxt away */

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1741

GEN12_CTX_SWITCH_DETAIL(upper_32_bits(csb)));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1906

head, upper_32_bits(csb), lower_32_bits(csb));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2759

*cs++ = upper_32_bits(pd_daddr);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

728

writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

730

writel(upper_32_bits(desc), execlists->submit_reg);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

429

*cs++ = upper_32_bits(pte | addr);

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

107

intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val));

sys/dev/pci/drm/i915/gt/intel_gt.c

340

upper_32_bits(fault_addr), lower_32_bits(fault_addr),

sys/dev/pci/drm/i915/gt/intel_gtt.c

629

intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));

sys/dev/pci/drm/i915/gt/intel_gtt.c

665

intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1424

*cs++ = upper_32_bits(i915_vma_offset(ce->vm->rsvd.vma));

sys/dev/pci/drm/i915/gt/intel_lrc_reg.h

36

(reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \

sys/dev/pci/drm/i915/gt/intel_lrc_reg.h

43

(reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \

sys/dev/pci/drm/i915/gt/intel_migrate.c

283

return upper_32_bits(mul_u32_u32(get_random_u32(), max));

sys/dev/pci/drm/i915/gt/intel_migrate.c

413

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/intel_migrate.c

446

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/intel_migrate.c

452

*cs++ = upper_32_bits(encode | it->dma);

sys/dev/pci/drm/i915/gt/intel_renderstate.c

75

s = upper_32_bits(r);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2745

*cs++ = upper_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2753

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3104

*cs++ = upper_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3111

*cs++ = upper_32_bits(i915_vma_offset(result));

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

175

*batch++ = upper_32_bits(hws_address(hws, rq));

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

185

*batch++ = upper_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1041

*cs++ = upper_32_bits(i915_vma_offset(scratch) + x);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1109

*cs++ = upper_32_bits(i915_vma_offset(b_before));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1125

*cs++ = upper_32_bits(i915_vma_offset(b_after));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1247

*cs++ = upper_32_bits(i915_vma_offset(batch));

sys/dev/pci/drm/i915/gt/selftest_rps.c

127

*cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));

sys/dev/pci/drm/i915/gt/selftest_rps.c

133

*cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));

sys/dev/pci/drm/i915/gt/selftest_tlb.c

113

*cs++ = upper_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_tlb.c

120

*cs++ = upper_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

575

*cs++ = upper_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

588

*cs++ = upper_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

601

*cs++ = upper_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

610

*cs++ = upper_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

878

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

274

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

128

*cmd++ = upper_32_bits(pkt->addr_in);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

131

*cmd++ = upper_32_bits(pkt->addr_out);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

32

*cs++ = upper_32_bits(pkt->addr_in);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

35

*cs++ = upper_32_bits(pkt->addr_out);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

867

FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, upper_32_bits(value)),

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

872

GEM_BUG_ON(len == 1 && upper_32_bits(value));

sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c

41

upper_32_bits(ggtt_offset),

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1184

u32 gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1304

gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2516

action[len++] = upper_32_bits(child->lrc.lrca);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2888

info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2909

info->wq_desc_hi = upper_32_bits(wq_desc_offset);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2911

info->wq_base_hi = upper_32_bits(wq_base_offset);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5677

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5722

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1034

GEM_BUG_ON(upper_32_bits(node->start));

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1035

GEM_BUG_ON(upper_32_bits(node->start + node->size - 1));

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1103

GEM_BUG_ON(upper_32_bits(offset) & 0xFFFF0000);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1105

intel_uncore_write_fw(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset));

sys/dev/pci/drm/i915/gvt/aperture_gm.c

154

intel_uncore_write(uncore, fence_reg_hi, upper_32_bits(value));

sys/dev/pci/drm/i915/gvt/cmd_parser.c

881

*cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]);

sys/dev/pci/drm/i915/i915_gpu_error.c

588

upper_32_bits(start), lower_32_bits(start),

sys/dev/pci/drm/i915/i915_gpu_error.c

589

upper_32_bits(end), lower_32_bits(end));

sys/dev/pci/drm/i915/i915_gpu_error.c

598

err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),

sys/dev/pci/drm/i915/i915_gpu_error.c

656

upper_32_bits(vma->gtt_offset),

sys/dev/pci/drm/i915/i915_perf.c

2113

*cs++ = upper_32_bits(delay_ticks);

sys/dev/pci/drm/i915/i915_vma.c

892

if (upper_32_bits(end - 1) &&

sys/dev/pci/drm/i915/i915_vma.h

181

GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma)));

sys/dev/pci/drm/i915/i915_vma.h

182

GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) +

sys/dev/pci/drm/i915/selftests/i915_random.h

49

return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro));

sys/dev/pci/drm/i915/selftests/i915_request.c

1148

*cmd++ = upper_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/selftests/igt_spinner.c

166

*batch++ = upper_32_bits(hws_address(hws, rq));

sys/dev/pci/drm/i915/selftests/igt_spinner.c

195

*batch++ = upper_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/soc/intel_gmch.c

106

upper_32_bits(i915->gmch.mch_res.start));

sys/dev/pci/drm/radeon/atombios_crtc.c

1386

upper_32_bits(fb_location));

sys/dev/pci/drm/radeon/atombios_crtc.c

1388

upper_32_bits(fb_location));

sys/dev/pci/drm/radeon/atombios_crtc.c

1601

WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/pci/drm/radeon/atombios_crtc.c

1602

WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/pci/drm/radeon/atombios_crtc.c

1604

WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/pci/drm/radeon/atombios_crtc.c

1605

WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/pci/drm/radeon/cik.c

3555

radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/pci/drm/radeon/cik.c

3567

radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));

sys/dev/pci/drm/radeon/cik.c

3595

radeon_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/radeon/cik.c

3621

radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);

sys/dev/pci/drm/radeon/cik.c

3683

radeon_ring_write(ring, upper_32_bits(src_offset));

sys/dev/pci/drm/radeon/cik.c

3685

radeon_ring_write(ring, upper_32_bits(dst_offset));

sys/dev/pci/drm/radeon/cik.c

3744

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

sys/dev/pci/drm/radeon/cik.c

3755

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/pci/drm/radeon/cik.c

4083

WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/cik.c

4096

WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/pci/drm/radeon/cik.c

4541

WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);

sys/dev/pci/drm/radeon/cik.c

4642

mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);

sys/dev/pci/drm/radeon/cik.c

4653

mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/pci/drm/radeon/cik.c

4681

mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/radeon/cik.c

4693

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/pci/drm/radeon/cik.c

6618

WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));

sys/dev/pci/drm/radeon/cik.c

6980

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/cik_sdma.c

145

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

sys/dev/pci/drm/radeon/cik_sdma.c

155

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/pci/drm/radeon/cik_sdma.c

208

radeon_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/radeon/cik_sdma.c

237

radeon_ring_write(ring, upper_32_bits(addr));

sys/dev/pci/drm/radeon/cik_sdma.c

400

upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);

sys/dev/pci/drm/radeon/cik_sdma.c

614

radeon_ring_write(ring, upper_32_bits(src_offset));

sys/dev/pci/drm/radeon/cik_sdma.c

616

radeon_ring_write(ring, upper_32_bits(dst_offset));

sys/dev/pci/drm/radeon/cik_sdma.c

670

radeon_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/pci/drm/radeon/cik_sdma.c

728

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/pci/drm/radeon/cik_sdma.c

817

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/pci/drm/radeon/cik_sdma.c

819

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/radeon/cik_sdma.c

858

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/radeon/cik_sdma.c

871

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/radeon/cik_sdma.c

911

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/pci/drm/radeon/cik_sdma.c

915

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/radeon/evergreen.c

1430

upper_32_bits(crtc_base));

sys/dev/pci/drm/radeon/evergreen.c

2769

upper_32_bits(rdev->mc.vram_start));

sys/dev/pci/drm/radeon/evergreen.c

2771

upper_32_bits(rdev->mc.vram_start));

sys/dev/pci/drm/radeon/evergreen.c

2779

WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));

sys/dev/pci/drm/radeon/evergreen.c

2948

radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));

sys/dev/pci/drm/radeon/evergreen.c

2959

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

sys/dev/pci/drm/radeon/evergreen.c

3103

WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/evergreen.c

4286

dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));

sys/dev/pci/drm/radeon/evergreen.c

4293

data = upper_32_bits(reg_list_mc_addr);

sys/dev/pci/drm/radeon/evergreen_cs.c

1825

ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1871

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

1906

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

1934

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2027

ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2107

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2168

ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/pci/drm/radeon/evergreen_cs.c

2206

ib[idx+3] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2254

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2276

ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/pci/drm/radeon/evergreen_cs.c

2298

ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/pci/drm/radeon/evergreen_cs.c

2429

(upper_32_bits(offset64) & 0xff);

sys/dev/pci/drm/radeon/evergreen_cs.c

2509

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2528

ib[idx+4] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2557

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2582

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2609

ib[idx+4] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2658

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2691

ib[idx + 1] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2716

ib[idx + 2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2743

ib[idx + 6] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2932

ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2976

ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2977

ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2992

ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

2998

ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3035

ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3036

ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3047

ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3049

ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3085

ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3086

ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3087

ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3125

ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3141

ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3145

ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3187

ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3203

ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3209

ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3274

ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/evergreen_cs.c

3296

ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;

sys/dev/pci/drm/radeon/evergreen_dma.c

142

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

sys/dev/pci/drm/radeon/evergreen_dma.c

143

radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

sys/dev/pci/drm/radeon/evergreen_dma.c

48

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));

sys/dev/pci/drm/radeon/evergreen_dma.c

78

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

sys/dev/pci/drm/radeon/evergreen_dma.c

89

radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));

sys/dev/pci/drm/radeon/ni.c

1394

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));

sys/dev/pci/drm/radeon/ni.c

1424

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

sys/dev/pci/drm/radeon/ni.c

1678

WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);

sys/dev/pci/drm/radeon/ni_dma.c

134

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

sys/dev/pci/drm/radeon/ni_dma.c

145

radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));

sys/dev/pci/drm/radeon/ni_dma.c

222

upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);

sys/dev/pci/drm/radeon/ni_dma.c

330

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/pci/drm/radeon/ni_dma.c

331

ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;

sys/dev/pci/drm/radeon/ni_dma.c

370

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/pci/drm/radeon/ni_dma.c

382

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/radeon/ni_dma.c

422

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/pci/drm/radeon/ni_dma.c

426

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/radeon/r100.c

3869

upper_32_bits(rdev->mc.agp_base) & 0xff);

sys/dev/pci/drm/radeon/r300.c

109

((upper_32_bits(addr) & 0xff) << 24);

sys/dev/pci/drm/radeon/r300.c

1341

upper_32_bits(rdev->mc.agp_base) & 0xff);

sys/dev/pci/drm/radeon/r520.c

157

S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));

sys/dev/pci/drm/radeon/r600.c

2750

WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/r600.c

2889

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));

sys/dev/pci/drm/radeon/r600.c

2939

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);

sys/dev/pci/drm/radeon/r600.c

2999

tmp = upper_32_bits(src_offset) & 0xff;

sys/dev/pci/drm/radeon/r600.c

3006

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

sys/dev/pci/drm/radeon/r600.c

3381

radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));

sys/dev/pci/drm/radeon/r600.c

3392

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

sys/dev/pci/drm/radeon/r600.c

3719

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/r600_cs.c

1683

ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/pci/drm/radeon/r600_cs.c

1724

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

1776

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

1820

ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/pci/drm/radeon/r600_cs.c

1850

ib[idx+3] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

1888

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

1910

ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/pci/drm/radeon/r600_cs.c

2017

(upper_32_bits(offset64) & 0xff);

sys/dev/pci/drm/radeon/r600_cs.c

2162

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2182

ib[idx+4] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2211

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2236

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2260

ib[idx+4] = upper_32_bits(offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2425

ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2457

ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2463

ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2479

ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2480

ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2490

ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/pci/drm/radeon/r600_cs.c

2491

ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;

sys/dev/pci/drm/radeon/r600_cs.c

2524

ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;

sys/dev/pci/drm/radeon/r600_dma.c

143

upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/r600_dma.c

255

radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);

sys/dev/pci/drm/radeon/r600_dma.c

295

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));

sys/dev/pci/drm/radeon/r600_dma.c

322

radeon_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/pci/drm/radeon/r600_dma.c

360

ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;

sys/dev/pci/drm/radeon/r600_dma.c

415

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

sys/dev/pci/drm/radeon/r600_dma.c

426

radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));

sys/dev/pci/drm/radeon/r600_dma.c

478

radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |

sys/dev/pci/drm/radeon/r600_dma.c

479

(upper_32_bits(src_offset) & 0xff)));

sys/dev/pci/drm/radeon/r600_dpm.c

523

WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask));

sys/dev/pci/drm/radeon/radeon_cursor.c

100

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/pci/drm/radeon/radeon_cursor.c

111

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/pci/drm/radeon/radeon_cursor.c

114

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/pci/drm/radeon/radeon_vce.c

412

ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));

sys/dev/pci/drm/radeon/radeon_vce.c

466

ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));

sys/dev/pci/drm/radeon/radeon_vce.c

753

radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr)));

sys/dev/pci/drm/radeon/radeon_vce.c

772

radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr)));

sys/dev/pci/drm/radeon/rs400.c

166

tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;

sys/dev/pci/drm/radeon/rs400.c

224

((upper_32_bits(addr) & 0xff) << 4);

sys/dev/pci/drm/radeon/rv515.c

360

upper_32_bits(rdev->mc.vram_start));

sys/dev/pci/drm/radeon/rv515.c

362

upper_32_bits(rdev->mc.vram_start));

sys/dev/pci/drm/radeon/rv515.c

365

upper_32_bits(rdev->mc.vram_start));

sys/dev/pci/drm/radeon/rv515.c

367

upper_32_bits(rdev->mc.vram_start));

sys/dev/pci/drm/radeon/rv515.c

464

S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));

sys/dev/pci/drm/radeon/rv770.c

819

WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/pci/drm/radeon/rv770.c

820

WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/pci/drm/radeon/rv770.c

822

WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/pci/drm/radeon/rv770.c

823

WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/pci/drm/radeon/rv770_dma.c

77

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

sys/dev/pci/drm/radeon/rv770_dma.c

78

radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

sys/dev/pci/drm/radeon/si.c

3372

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));

sys/dev/pci/drm/radeon/si.c

3405

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

sys/dev/pci/drm/radeon/si.c

3418

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/pci/drm/radeon/si.c

3663

WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/si.c

3694

WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/si.c

3718

WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/si.c

6003

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/si_dma.c

121

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/pci/drm/radeon/si_dma.c

133

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/radeon/si_dma.c

173

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/pci/drm/radeon/si_dma.c

177

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/pci/drm/radeon/si_dma.c

265

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

sys/dev/pci/drm/radeon/si_dma.c

266

radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

sys/dev/pci/drm/radeon/si_dma.c

82

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/pci/drm/radeon/si_dma.c

83

ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;

sys/dev/pci/drm/radeon/uvd_v1_0.c

364

WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |

sys/dev/pci/drm/radeon/uvd_v2_2.c

50

radeon_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/pci/drm/radeon/vce_v1_0.c

301

WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/radeon/vce_v1_0.c

308

WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));