Symbol: update_state
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1008
update_state->pg_pipe_res_update[PG_OPTC][0] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1013
if (!update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1014
!update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1016
update_state->pg_pipe_res_update[PG_HUBP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1017
update_state->pg_pipe_res_update[PG_DPP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1027
struct pg_block_update *update_state)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1033
memset(update_state, 0, sizeof(struct pg_block_update));
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1048
update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1051
update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1054
update_state->pg_pipe_res_update[j][new_pipe->plane_res.mpcc_inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1057
update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1060
update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1063
update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1066
update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1075
update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1080
update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1085
update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1090
update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1095
update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1100
update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1107
update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1118
update_state->pg_res_update[PG_HPO] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1121
update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1128
update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1129
update_state->pg_pipe_res_update[PG_HUBP][new_pipe->stream_res.dsc->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1130
update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1136
update_state->pg_pipe_res_update[PG_HUBP][j] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1137
update_state->pg_pipe_res_update[PG_DPP][j] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1144
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1145
update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1147
update_state->pg_pipe_res_update[PG_HUBP][j] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1148
update_state->pg_pipe_res_update[PG_DPP][j] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1181
struct pg_block_update *update_state)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1191
if (update_state->pg_res_update[PG_HPO]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1198
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1199
update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1206
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1213
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1218
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1219
update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1258
struct pg_block_update *update_state)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1274
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1281
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1282
update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1288
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1294
if (update_state->pg_res_update[PG_HPO]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1300
struct pg_block_update *update_state, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1310
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1311
update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1315
if (update_state->pg_pipe_res_update[PG_DPSTREAM][i])
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1321
if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i])
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1327
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1340
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1341
update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1345
if (update_state->pg_pipe_res_update[PG_DPSTREAM][i])
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1351
if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i])
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1565
static void dcn35_calc_blocks_to_ungate_for_hw_release(struct dc *dc, struct pg_block_update *update_state)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1569
memset(update_state, 0, sizeof(struct pg_block_update));
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1573
update_state->pg_pipe_res_update[j][i] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1575
update_state->pg_res_update[PG_HPO] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1576
update_state->pg_res_update[PG_DWB] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
923
struct pg_block_update *update_state)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
931
memset(update_state, 0, sizeof(struct pg_block_update));
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
942
update_state->pg_res_update[PG_HPO] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
944
update_state->pg_res_update[PG_DWB] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
950
update_state->pg_pipe_res_update[j][i] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
956
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
959
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
962
update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
965
update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
967
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
968
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
974
update_state->pg_pipe_res_update[PG_HUBP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
975
update_state->pg_pipe_res_update[PG_DPP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
982
update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
985
update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
989
update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
991
update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
998
update_state->pg_pipe_res_update[PG_OPTC][i] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
67
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
69
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
71
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
73
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
75
struct pg_block_update *update_state, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
100
struct pg_block_update *update_state)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
109
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
114
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
115
update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
153
struct pg_block_update *update_state)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
171
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
172
update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
177
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
39
struct pg_block_update *update_state)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
43
dcn35_calc_blocks_to_gate(dc, context, update_state);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
46
if (!update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
47
!update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
49
update_state->pg_pipe_res_update[PG_HUBP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
50
update_state->pg_pipe_res_update[PG_DPP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
59
struct pg_block_update *update_state)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
63
dcn35_calc_blocks_to_ungate(dc, context, update_state);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
66
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
67
update_state->pg_pipe_res_update[PG_DPP][i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
69
update_state->pg_pipe_res_update[PG_HUBP][j] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
70
update_state->pg_pipe_res_update[PG_DPP][j] = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
33
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
35
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
37
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
39
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
441
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
443
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
445
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
447
struct pg_block_update *update_state);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
449
struct pg_block_update *update_state, bool power_on);
usr.bin/systat/cache.c
160
update_state(old, st, r);
usr.bin/systat/cache.c
42
void update_state(struct sc_ent *, struct pfsync_state *, double);