Symbol: DECLARE_BITMAP
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1080
DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1031
DECLARE_BITMAP(cp_queue_bitmap, AMDGPU_MAX_QUEUES);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
118
DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
397
DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
487
DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.h
37
DECLARE_BITMAP(used, AMDGPU_MAX_SEQ64_SLOTS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_utils.h
45
DECLARE_BITMAP(bmap, NAME##_BITMAP_BITS); \
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
258
DECLARE_BITMAP(sdma_bitmap, KFD_MAX_SDMA_QUEUES);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
259
DECLARE_BITMAP(xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
244
DECLARE_BITMAP(reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
882
DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1348
DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1538
DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3465
DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3799
DECLARE_BITMAP(bitmap_access, MAX_GPU_INSTANCE);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3800
DECLARE_BITMAP(bitmap_aip, MAX_GPU_INSTANCE);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.h
137
DECLARE_BITMAP(bitmap_access, MAX_GPU_INSTANCE);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.h
138
DECLARE_BITMAP(bitmap_aip, MAX_GPU_INSTANCE);
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
117
DECLARE_BITMAP(cp_queue_bitmap, AMDGPU_MAX_QUEUES);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
434
DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
435
DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
539
DECLARE_BITMAP(cap_map, SMU_FEATURE_CAP_ID__COUNT);
sys/dev/pci/drm/apple/afk.h
42
DECLARE_BITMAP(cmd_map, MAX_PENDING_CMDS);
sys/dev/pci/drm/apple/dcp-internal.h
151
DECLARE_BITMAP(memdesc_map, DCP_MAX_MAPPINGS);
sys/dev/pci/drm/display/drm_dp_tunnel.c
116
static const DECLARE_BITMAP(dptun_info_regs, 64) = {
sys/dev/pci/drm/i915/display/intel_display_device.h
118
DECLARE_BITMAP(bitmap, __NUM_PLATFORMS);
sys/dev/pci/drm/i915/display/intel_display_power.h
129
DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
sys/dev/pci/drm/i915/gvt/gtt.h
261
DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE);
sys/dev/pci/drm/i915/gvt/gvt.h
116
DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
sys/dev/pci/drm/i915/gvt/gvt.h
160
DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gvt/gvt.h
161
DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
sys/dev/pci/drm/i915/gvt/gvt.h
187
DECLARE_BITMAP(status, INTEL_VGPU_STATUS_NR_BITS);
sys/dev/pci/drm/i915/gvt/interrupt.c
45
DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH);
sys/dev/pci/drm/i915/gvt/interrupt.h
188
DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX);
sys/dev/pci/drm/i915/gvt/scheduler.h
102
DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
sys/dev/pci/drm/radeon/radeon.h
695
DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);