regress/lib/libc/qsort/qsort_test.c

436

if (timing)

regress/lib/libc/qsort/qsort_test.c

439

if (timing) {

regress/lib/libc/qsort/qsort_test.c

57

static bool dump_table, timing, verbose;

regress/lib/libc/qsort/qsort_test.c

621

if (timing)

regress/lib/libc/qsort/qsort_test.c

624

if (timing)

regress/lib/libc/qsort/qsort_test.c

638

if (timing) {

regress/lib/libc/qsort/qsort_test.c

750

timing = true;

sbin/bioctl/bioctl.c

1189

struct timing timing;

sbin/bioctl/bioctl.c

1225

errstr = str2patrol(arg, &timing);

sbin/bioctl/bioctl.c

1228

bp.bp_autoival = timing.interval;

sbin/bioctl/bioctl.c

1229

bp.bp_autonext = timing.start;

sbin/bioctl/bioctl.c

333

str2patrol(const char *string, struct timing *timing)

sbin/bioctl/bioctl.c

338

timing->interval = 0;

sbin/bioctl/bioctl.c

339

timing->start = 0;

sbin/bioctl/bioctl.c

352

timing->interval = strtonum(interval, -1, INT_MAX, &errstr);

sbin/bioctl/bioctl.c

357

timing->start = strtonum(start, 0, INT_MAX, &errstr);

sbin/bioctl/bioctl.c

64

const char *str2patrol(const char *, struct timing *);

sbin/ping/ping.c

1141

if (timing) {

sbin/ping/ping.c

193

int timing; /* flag to do timing */

sbin/ping/ping.c

580

timing = 1;

sys/arch/armv7/omap/ommmc.c

708

ommmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)

sys/arch/armv7/omap/ommmc.c

751

if ((timing == SDMMC_TIMING_HIGHSPEED) && (sc->sc_flags & FL_HSS))

sys/arch/octeon/dev/octmmc.c

527

octmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)

sys/arch/octeon/dev/octmmc.c

549

if (timing)

sys/dev/fdt/amlmmc.c

503

amlmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)

sys/dev/fdt/amlmmc.c

521

if (timing == SDMMC_TIMING_MMC_DDR52)

sys/dev/fdt/amlmmc.c

536

if (timing == SDMMC_TIMING_MMC_DDR52)

sys/dev/fdt/amlmmc.c

769

amlmmc_execute_tuning(sdmmc_chipset_handle_t sch, int timing)

sys/dev/fdt/amlmmc.c

777

switch (timing) {

sys/dev/fdt/cdsdhc.c

144

cdsdhc_bus_clock_pre(struct sdhc_softc *sc_sdhc, int freq, int timing)

sys/dev/fdt/cdsdhc.c

149

switch (timing) {

sys/dev/fdt/dwmmc.c

660

dwmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)

sys/dev/fdt/dwmshc.c

322

dwmshc_clock_pre(struct sdhc_softc *sdhc, int freq, int timing)

sys/dev/fdt/dwmshc.c

332

if (timing == hs400es) {

sys/dev/fdt/dwmshc.c

366

dwmshc_clock_post(struct sdhc_softc *sdhc, int freq, int timing)

sys/dev/fdt/dwmshc.c

374

if (timing == SDMMC_TIMING_LEGACY) { /* disable dll */

sys/dev/fdt/dwmshc.c

410

if (timing >= SDMMC_TIMING_MMC_HS200) {

sys/dev/fdt/dwmshc.c

416

timing == SDMMC_TIMING_MMC_HS400) {

sys/dev/fdt/imxesdhc.c

683

imxesdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)

sys/dev/fdt/sdhc_fdt.c

370

sdhc_fdt_xenon_bus_clock_post(struct sdhc_softc *ssc, int freq, int timing)

sys/dev/fdt/sdhc_fdt.c

397

if (timing == SDMMC_TIMING_LEGACY)

sys/dev/fdt/sdhc_fdt.c

453

if (timing == SDMMC_TIMING_LEGACY ||

sys/dev/fdt/sdhc_fdt.c

454

timing == SDMMC_TIMING_HIGHSPEED || sc->sc_slow_mode)

sys/dev/fdt/sximmc.c

739

sximmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)

sys/dev/ic/rtsx.c

659

rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)

sys/dev/ic/w83l518d_sdmmc.c

281

wb_sdmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10707

get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state)))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10730

= get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6387

dst.width = stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6388

dst.height = stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6407

dst.x = (stream->timing.h_addressable - dst.width) / 2;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6408

dst.y = (stream->timing.v_addressable - dst.height) / 2;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6617

struct dc_crtc_timing *timing_out = &stream->timing;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6661

timing_out->vic = old_stream->timing.vic;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6662

timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6663

timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

680

stream->adjust.v_total_max : stream->timing.v_total;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

681

refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

682

100LL, (v_total * stream->timing.h_total));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6836

master->timing.flags.VSYNC_POSITIVE_POLARITY ?

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6851

refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6852

(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7012

stream->timing.flags.DSC = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7057

&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7066

&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7069

stream->timing.dsc_cfg = dsc_cfg;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7070

stream->timing.flags.DSC = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7071

stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7081

&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7084

stream->timing.dsc_cfg = dsc_cfg;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7085

stream->timing.flags.DSC = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7124

&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7126

&stream->timing.dsc_cfg)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7127

stream->timing.flags.DSC = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7132

timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7144

&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7146

&stream->timing.dsc_cfg)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7147

stream->timing.flags.DSC = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7156

stream->timing.flags.DSC = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7158

if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7159

stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7161

if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7162

stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7164

if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7165

stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7232

stream->timing.flags.LTE_340MCSC_SCRAMBLE =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7298

stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7300

stream->timing = *aconnector->timing_requested;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7940

dc_pixel_encoding_to_str(stream->timing.pixel_encoding),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7941

dc_color_depth_to_str(stream->timing.display_color_depth),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8354

if (stream->timing.flags.DSC != 1) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9101

struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9105

timing = &acrtc_state->stream->timing;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9127

timing->v_total *

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9128

timing->h_total,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9129

timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9139

timing->v_total *

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9140

timing->h_total,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9141

timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9389

if (!new_stream->timing.h_total || !new_stream->timing.v_total)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9478

if (!new_stream->timing.h_total || !new_stream->timing.v_total)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1104

switch (dm_crtc_state->stream->timing.display_color_depth) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1890

pipe_ctx->stream->timing.h_addressable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2074

pipe_ctx->stream->timing.v_addressable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1302

&& pipe_ctx->stream->timing.display_color_depth != requestColorDepth)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1304

&& pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1307

pipe_ctx->stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1308

pipe_ctx->stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1311

pipe_ctx->stream->timing.display_color_depth = requestColorDepth;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1312

pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1319

*aconnector->timing_requested = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1233

stream->timing.flags.DSC = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1235

params[count].timing = &stream->timing;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1246

dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1253

&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1256

params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1541

if (stream->timing.flags.DSC == 1)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1786

dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1792

&stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1874

dc_bandwidth_in_kbps_from_timing(&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1952

&stream->timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1954

&stream->timing.dsc_cfg)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1955

stream->timing.flags.DSC = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1963

switch (stream->timing.pixel_encoding) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1979

((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

874

struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

924

memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

930

params[i].timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

932

&params[i].timing->dsc_cfg)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

933

params[i].timing->flags.DSC = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

936

params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

938

params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

941

params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

944

params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

946

params[i].timing->flags.DSC = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

948

params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

960

params[i].timing->flags.DSC,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

961

params[i].timing->dsc_cfg.bits_per_pixel,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

982

(int) kbps, param.timing,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

156

stream->timing.pix_clk_100hz * (uint64_t)100),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

157

stream->timing.v_total),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

158

stream->timing.h_total);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

165

link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

426

__entry->stream_w = stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

427

__entry->stream_h = stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2822

data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2823

data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2824

data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_100hz, 10000);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2921

data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2922

data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2923

pixel_clock_100hz = pipe[i].stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2924

if (pipe[i].stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2990

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2992

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

101

uint32_t vertical_total_min = stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

106

vertical_blank_in_pixels = stream->timing.h_total *

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

108

- stream->timing.v_addressable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

110

* 10000 / stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

169

cfg->v_refresh = stream->timing.pix_clk_100hz * 100;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

170

cfg->v_refresh /= stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

171

cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

172

/ stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

178

const struct dc_crtc_timing *timing =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

179

&context->streams[0]->timing;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

183

timing->h_total * 10000 / timing->pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

496

if (pipe->stream->timing.h_addressable == width &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

497

pipe->stream->timing.v_addressable == height &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

575

pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

578

refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

579

curr_pipe_ctx->stream->timing.v_total * (uint64_t)curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

580

refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

581

refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

365

&stream->timing, dc_link_get_highest_encoding_format(link));

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

401

if (pipe->stream->timing.h_addressable == width &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

402

pipe->stream->timing.v_addressable == height &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

477

pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

480

refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

481

curr_pipe_ctx->stream->timing.v_total

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

482

* (uint64_t) curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

483

refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

484

refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2267

context->streams[i]->timing.h_addressable,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2268

context->streams[i]->timing.v_addressable,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2269

context->streams[i]->timing.h_total,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2270

context->streams[i]->timing.v_total,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2271

context->streams[i]->timing.pix_clk_100hz / 10);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3332

struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3333

uint32_t old_dsc_enabled = stream->timing.flags.DSC;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3341

stream->timing.dsc_cfg = *update->dsc_config;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3342

stream->timing.flags.DSC = enable_dsc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3345

stream->timing.dsc_cfg = old_dsc_cfg;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3346

stream->timing.flags.DSC = old_dsc_enabled;

sys/dev/pci/drm/amd/display/dc/core/dc.c

718

param.windowa_x_end = pipe->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

719

param.windowa_y_end = pipe->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

722

param.windowb_x_end = pipe->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

723

param.windowb_y_end = pipe->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

736

param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;

sys/dev/pci/drm/amd/display/dc/core/dc.c

814

stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1417

enum dc_color_depth color_depth = otg_master->stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1446

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1468

pipe_ctx->stream->dst.x += timing->h_border_left;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1469

pipe_ctx->stream->dst.y += timing->v_border_top;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1635

pipe_ctx->stream->dst.x -= timing->h_border_left;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1636

pipe_ctx->stream->dst.y -= timing->v_border_top;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2137

const struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2146

timing = &otg_master->stream->timing;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2148

h_active = timing->h_addressable +

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2149

timing->h_border_left +

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2150

timing->h_border_right +

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2156

otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2163

timing->pixel_encoding == PIXEL_ENCODING_YCBCR422;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2184

odm_slice_dst.height = stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2185

stream->timing.v_border_bottom +

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2186

stream->timing.v_border_top;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2205

opp, pipe_ctx->stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3420

&cur_stream->timing,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3421

&new_stream->timing,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3587

static int get_norm_pix_clk(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3589

uint32_t pix_clk = timing->pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3592

if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3594

if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3595

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3625

&stream->timing) / 10;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3628

stream->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3630

if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3758

if (dc_validate_boot_timing(dc, stream->sink, &stream->timing)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4294

pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz = stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4408

unsigned int vic = pipe_ctx->stream->timing.vic;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4409

unsigned int rid = pipe_ctx->stream->timing.rid;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4410

unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4423

color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4438

switch (stream->timing.pixel_encoding) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4505

aspect = stream->timing.aspect_ratio;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4563

if (pipe_ctx->stream->timing.hdmi_vic != 0)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4565

format = stream->timing.timing_3d_format;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4569

switch (pipe_ctx->stream->timing.hdmi_vic) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4618

hdmi_info.bits.bar_top = stream->timing.v_border_top;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4619

hdmi_info.bits.bar_bottom = (stream->timing.v_total

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4620

- stream->timing.v_border_bottom + 1);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4621

hdmi_info.bits.bar_left = stream->timing.h_border_left;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4622

hdmi_info.bits.bar_right = (stream->timing.h_total

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4623

- stream->timing.h_border_right + 1);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4717

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4725

const struct dc_crtc_timing *tg = timing;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4754

&stream->timing,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4944

stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4949

switch (stream->timing.display_color_depth) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5078

if (!tg->funcs->validate_timing(tg, &stream->timing))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5093

&stream->timing);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5408

h_blank_start = stream->timing.h_total - stream->timing.h_front_porch;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5409

h_blank_end = h_blank_start - stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5415

divisible = (stream->timing.h_total % 2 == 0) &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5418

(stream->timing.h_sync_width % 2 == 0);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5472

if (sec_pipe->stream->timing.flags.DSC == 1) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

573

stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

574

stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

576

if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

577

stream1->timing.v_total > 60)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

579

if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

580

stream2->timing.v_total > 60)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

583

stream1->timing.h_total *

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

584

stream1->timing.v_total *

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

585

stream2->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

586

frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

587

frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

588

frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

605

if (stream1->timing.h_total != stream2->timing.h_total)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

608

if (stream1->timing.v_total != stream2->timing.v_total)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

611

if (stream1->timing.h_addressable

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

612

!= stream2->timing.h_addressable)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

615

if (stream1->timing.v_addressable

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

616

!= stream2->timing.v_addressable)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

619

if (stream1->timing.v_front_porch

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

620

!= stream2->timing.v_front_porch)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

623

if (stream1->timing.pix_clk_100hz

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

624

!= stream2->timing.pix_clk_100hz)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

945

*dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1068

return (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*(long long)stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1114

if (stream->timing.v_total * stream->timing.h_total == 0)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1117

int current_refresh_hz = (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*(long long)stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

112

stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1125

int safe_refresh_v_total = (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, safe_refresh_hz*(long long)stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1128

return (((int) stream->timing.v_total - safe_refresh_v_total) >= 0) ? (stream->timing.v_total - safe_refresh_v_total) : 0;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1130

return ((safe_refresh_v_total - (int) stream->timing.v_total) >= 0) ? (safe_refresh_v_total - stream->timing.v_total) : 0;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

114

memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

115

stream->timing.dsc_cfg.num_slices_h = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

116

stream->timing.dsc_cfg.num_slices_v = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

117

stream->timing.dsc_cfg.bits_per_pixel = 128;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

118

stream->timing.dsc_cfg.block_pred_enable = 1;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

119

stream->timing.dsc_cfg.linebuf_depth = 9;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

120

stream->timing.dsc_cfg.version_minor = 2;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

121

stream->timing.dsc_cfg.ycbcr422_simple = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

57

(stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

844

stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

845

stream->timing.h_total,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

846

stream->timing.v_total,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

847

dc_pixel_encoding_to_str(stream->timing.pixel_encoding),

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

848

dc_color_depth_to_str(stream->timing.display_color_depth));

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

855

stream->timing.flags.DSC,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

856

stream->timing.dsc_cfg.mst_pbn);

sys/dev/pci/drm/amd/display/dc/dc.h

1946

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

488

uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

490

config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

582

struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

584

struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

600

phantom_timing = &phantom_stream->timing;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

681

pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

682

pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

683

vblank_pipe->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

684

pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

685

pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

689

vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

732

phantom_timing0 = &phantom_stream0->timing;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

733

phantom_timing1 = &phantom_stream1->timing;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

785

struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

792

phantom_timing = &phantom_stream->timing;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

795

pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

796

pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

797

pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

100

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

107

void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

76

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

85

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

89

uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

93

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

131

stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

134

stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

140

spl_in->basic_out.use_two_pixels_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

198

struct dc_crtc_timing timing;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

564

(params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ||

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

565

(params->timing->flags.DSC && params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR422

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

566

&& !params->timing->dsc_cfg.ycbcr422_simple)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

539

cfg->v_refresh = stream->timing.pix_clk_100hz * 100;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

540

cfg->v_refresh /= stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

541

cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

542

/ stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

558

vertical_blank_in_pixels = stream->timing.h_total *

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

559

(stream->timing.v_total

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

560

- stream->timing.v_addressable);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

563

* 10000 / stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

660

const struct dc_crtc_timing *timing =

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

661

&context->streams[0]->timing;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

665

pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

929

&stream->timing);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

934

&stream->timing,

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

940

enc110, &stream->timing);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

944

is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

966

m_vid_l *= param->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

382

copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

178

copy_settings_data->flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1115

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1123

ASSERT(timing != NULL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1125

if (!timing)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1128

hsync_offset = timing->h_border_right + timing->h_front_porch;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1129

h_sync_start = timing->h_addressable + hsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1132

if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1136

if (timing->flags.INTERLACE == 1)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1144

if (timing->h_total > tg110->max_h_total ||

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1145

timing->v_total > tg110->max_v_total)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1148

h_blank = (timing->h_total - timing->h_addressable -

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1149

timing->h_border_right -

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1150

timing->h_border_left);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1155

if (timing->h_front_porch < tg110->min_h_front_porch)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1159

timing->h_addressable -

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1160

timing->h_border_right -

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1161

timing->h_sync_width);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1412

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1432

if ((timing->v_sync_width + timing->v_front_porch) <= 3) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1953

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1963

dce110_timing_generator_program_timing_generator(tg, timing);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1965

dce110_timing_generator_program_blanking(tg, timing);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2014

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2016

return dce110_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2031

bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2033

return timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

256

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

267

if (timing->flags.HORZ_COUNT_BY_TWO)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

602

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

604

uint32_t vsync_offset = timing->v_border_bottom +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

605

timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

606

uint32_t v_sync_start = timing->v_addressable + vsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

608

uint32_t hsync_offset = timing->h_border_right +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

609

timing->h_front_porch;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

610

uint32_t h_sync_start = timing->h_addressable + hsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

622

timing->h_total - 1,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

631

timing->v_total - 1,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

643

timing->v_total - 1,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

652

timing->v_total - 1,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

660

tmp = timing->h_total -

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

661

(h_sync_start + timing->h_border_left);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

669

tmp = tmp + timing->h_addressable +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

67

struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

670

timing->h_border_left + timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

683

tmp = timing->v_total - (v_sync_start + timing->v_border_top);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

69

if (timing->flags.INTERLACE == 1) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

691

tmp = tmp + timing->v_addressable + timing->v_border_top +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

692

timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

70

if (timing->v_front_porch < 2)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

71

timing->v_front_porch = 2;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

73

if (timing->v_front_porch < 1)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

74

timing->v_front_porch = 1;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

129

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

203

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

247

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

259

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

274

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

292

bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

243

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

245

uint32_t vsync_offset = timing->v_border_bottom +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

246

timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

247

uint32_t v_sync_start = timing->v_addressable + vsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

249

uint32_t hsync_offset = timing->h_border_right +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

250

timing->h_front_porch;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

251

uint32_t h_sync_start = timing->h_addressable + hsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

262

timing->h_total - 1,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

271

timing->v_total - 1,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

279

tmp = timing->h_total -

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

280

(h_sync_start + timing->h_border_left);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

288

tmp = tmp + timing->h_addressable +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

289

timing->h_border_left + timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

302

tmp = timing->v_total - (v_sync_start + timing->v_border_top);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

310

tmp = tmp + timing->v_addressable + timing->v_border_top +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

311

timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

325

timing->h_sync_width,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

332

if (timing->flags.HSYNC_POSITIVE_POLARITY) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

351

timing->v_sync_width,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

358

if (timing->flags.VSYNC_POSITIVE_POLARITY) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

377

timing->flags.INTERLACE,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

386

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

392

if ((timing->v_sync_width + timing->v_front_porch) <= 3) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

436

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

446

dce110_timing_generator_program_timing_generator(tg, timing);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

448

dce110_timing_generator_v_program_blanking(tg, timing);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

103

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

106

uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

108

(timing->v_total - timing->v_addressable -

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

109

timing->v_border_top - timing->v_border_bottom) *

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

115

timing,

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

121

timing->h_sync_width < tg110->min_h_sync_width ||

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

122

timing->v_sync_width < tg110->min_v_sync_width)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

129

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

131

return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

430

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

434

uint32_t vsync_offset = timing->v_border_bottom +

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

435

timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

436

uint32_t v_sync_start = timing->v_addressable + vsync_offset;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

438

uint32_t hsync_offset = timing->h_border_right +

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

439

timing->h_front_porch;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

440

uint32_t h_sync_start = timing->h_addressable + hsync_offset;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

446

timing->h_total - 1);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

451

timing->v_total - 1);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

459

timing->v_total - 1);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

464

timing->v_total - 1);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

466

tmp1 = timing->h_total -

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

467

(h_sync_start + timing->h_border_left);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

468

tmp2 = tmp1 + timing->h_addressable +

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

469

timing->h_border_left + timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

476

tmp1 = timing->v_total - (v_sync_start + timing->v_border_top);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

477

tmp2 = tmp1 + timing->v_addressable + timing->v_border_top +

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

478

timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

624

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

628

timing->v_total - timing->v_addressable -

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

629

timing->v_border_bottom - timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

695

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

705

dce110_timing_generator_program_timing_generator(tg, timing);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

707

dce120_timing_generator_program_blanking(tg, timing);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

748

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

109

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

119

program_pix_dur(tg, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

121

dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios);

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

127

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

139

if ((timing->v_sync_width + timing->v_front_porch) <= 3) {

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

109

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

119

program_pix_dur(tg, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

121

dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios);

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

127

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

147

if ((timing->v_sync_width + timing->v_front_porch) <= 3) {

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

800

&stream->timing);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

805

&stream->timing,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

812

enc10, &stream->timing);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

815

is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

972

if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

980

m_vid_l *= param->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

459

static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

461

bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

463

two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

464

&& !timing->dsc_cfg.ycbcr422_simple);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

482

if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) {

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

490

m_vid_l *= param->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

277

static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

279

bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

281

two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

282

&& !timing->dsc_cfg.ycbcr422_simple);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

312

if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) {

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

321

m_vid_l *= param->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

235

static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

237

bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

239

two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

240

&& !timing->dsc_cfg.ycbcr422_simple);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

259

if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

269

m_vid_l *= param->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

267

static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

269

bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

271

two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

272

&& !timing->dsc_cfg.ycbcr422_simple);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

291

if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

301

m_vid_l *= param->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

254

static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

256

bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

258

two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

259

&& !timing->dsc_cfg.ycbcr422_simple);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

277

if (is_two_pixels_per_containter(&param->timing)) {

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

284

m_vid_l *= param->timing.pix_clk_100hz / pix_per_container / 10;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1030

v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1036

switch (pipe->stream->timing.display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1214

pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1215

pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1216

vesa_sync_start = pipe->stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1217

pipe->stream->timing.v_border_bottom +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1218

pipe->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1220

asic_blank_end = (pipe->stream->timing.v_total -

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1222

pipe->stream->timing.v_border_top)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1223

* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1226

(pipe->stream->timing.v_border_top +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1227

pipe->stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1228

pipe->stream->timing.v_border_bottom)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1229

* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1244

(pipe->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1246

pipe->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1255

hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1256

hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

422

input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

423

+ pipe->stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

431

input->dest.htotal = pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

432

input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

434

- pipe->stream->timing.h_addressable

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

435

- pipe->stream->timing.h_border_left

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

436

- pipe->stream->timing.h_border_right;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

438

input->dest.vtotal = pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

439

input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

441

- pipe->stream->timing.v_addressable

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

442

- pipe->stream->timing.v_border_bottom

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

443

- pipe->stream->timing.v_border_top;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

444

input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

736

hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

905

v->htotal[input_idx] = pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

906

v->vtotal[input_idx] = pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

907

v->vactive[input_idx] = pipe->stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

908

pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

909

v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

911

- pipe->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

912

v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

913

if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

920

v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

921

v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1206

&context->res_ctx.pipe_ctx[i].stream->timing,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1350

struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1359

v_total = timing->v_total;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1360

front_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1371

pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1373

pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1378

(v_total - timing->v_addressable

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1379

- timing->v_border_top - timing->v_border_bottom) / 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1388

pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1390

- timing->h_addressable

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1391

- timing->h_border_left

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1392

- timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1395

- timing->v_addressable

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1396

- timing->v_border_top

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1397

- timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1398

pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1401

timing->h_addressable + timing->h_border_left + timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1403

timing->v_addressable + timing->v_border_top + timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1404

pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1405

pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1406

if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1472

switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1502

switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1513

if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1514

!res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1525

if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1526

pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1553

pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1556

pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

284

static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

288

(((float)timing->h_total * 1000.0) /

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

289

((float)timing->pix_clk_100hz / 10.0));

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

296

static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

300

v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

301

v_blank = timing->v_total - v_active;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

302

v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

322

struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

329

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

331

num_lines = micro_sec_to_vert_lines(dcn3_14_ip.VBlankNomDefaultUS, timing);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

336

pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

338

v_back_porch = get_vertical_back_porch(timing);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

340

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

347

max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

369

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

374

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1002

refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1003

pipe->stream->timing.v_total * (uint64_t)pipe->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1004

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1005

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1344

if (stream->timing.pix_clk_100hz * 100 <= DCN3_2_VMIN_DISPCLK_HZ)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1761

&context->res_ctx.pipe_ctx[i].stream->timing,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1916

if (sec_pipe->stream->timing.flags.DSC == 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3403

refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3404

(uint64_t)pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3405

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3406

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3451

refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3452

pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3453

/ (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3461

refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3462

pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3463

/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3582

blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3583

(double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

502

(ref_pipe->stream->timing.pix_clk_100hz * 100) /

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

503

(double)ref_pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

539

phantom_stream->timing.v_addressable = phantom_vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

540

phantom_stream->timing.v_front_porch = 1;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

541

phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

542

phantom_stream->timing.v_front_porch +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

543

phantom_stream->timing.v_sync_width +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

545

phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

618

refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

619

pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

620

/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

631

!(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

647

unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

648

(double)(stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

746

microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

747

phantom->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

750

time_us = (microschedule_lines * phantom->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

751

(double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

765

vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

766

(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

767

vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

768

(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

769

vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

770

subvp_pipes[0]->stream->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

771

(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

772

vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

773

subvp_pipes[1]->stream->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

774

(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

852

main_timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

853

phantom_timing = &phantom_stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

854

drr_timing = &drr_pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

945

main_timing = &subvp_pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

946

phantom_timing = &phantom_stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

947

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

414

static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

418

(((float)timing->h_total * 1000.0) /

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

419

((float)timing->pix_clk_100hz / 10.0));

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

426

static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

430

v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

431

v_blank = timing->v_total - v_active;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

432

v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

454

struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

462

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

464

num_lines = micro_sec_to_vert_lines(dcn3_5_ip.VBlankNomDefaultUS, timing);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

465

v_back_porch = get_vertical_back_porch(timing);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

469

pipe->stream->adjust.v_total_min > timing->v_total) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

472

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

476

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

483

max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

505

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

511

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

447

static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

451

(((float)timing->h_total * 1000.0) /

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

452

((float)timing->pix_clk_100hz / 10.0));

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

459

static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

463

v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

464

v_blank = timing->v_total - v_active;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

465

v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

487

struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

495

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

497

num_lines = micro_sec_to_vert_lines(dcn3_51_ip.VBlankNomDefaultUS, timing);

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

498

v_back_porch = get_vertical_back_porch(timing);

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

502

pipe->stream->adjust.v_total_min > timing->v_total) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

505

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

509

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

516

max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

538

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

544

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2699

display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2700

if (display_cfg->timing.Interlace[k] == 1 && ptoi_supported == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2701

display_cfg->timing.PixelClock[k] = 2 * display_cfg->timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6175

struct dml_timing_cfg_st *timing,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6182

dml_float_t line_time_us = (dml_float_t) timing->HTotal[plane_idx] / timing->PixelClock[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6183

dml_uint_t vblank_actual = timing->VTotal[plane_idx] - timing->VActive[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6185

dml_uint_t vblank_nom_default_in_line = MicroSecToVertLines(vblank_nom_default_us, timing->HTotal[plane_idx],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6186

timing->PixelClock[plane_idx]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6194

timing->VTotal[plane_idx] - timing->VActive[plane_idx] - timing->VFrontPorch[plane_idx] + 2);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6201

if (timing->Interlace[plane_idx] && !ptoi_supported)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6207

dml_print("DML::%s: VBlankNom = %u\n", __func__, timing->VBlankNom[plane_idx]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6358

mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6367

myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6376

myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6378

myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6379

myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6380

myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6425

mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6443

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6444

mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.VRatioPreY[j][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6557

(mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]),

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6659

CalculateWatermarks_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6680

CalculateWatermarks_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6681

CalculateWatermarks_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6682

CalculateWatermarks_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6683

CalculateWatermarks_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6823

mode_lib->ms.ReadBandwidthLuma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * dml_ceil(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6824

mode_lib->ms.ReadBandwidthChroma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * dml_ceil(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k] / 2.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6832

* mode_lib->ms.cache_display_cfg.timing.HTotal[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6833

/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6838

* mode_lib->ms.cache_display_cfg.timing.HTotal[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6839

/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6896

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7010

CalculateSwathAndDETConfiguration_params->HActive = mode_lib->ms.cache_display_cfg.timing.HActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7050

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7059

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7073

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7082

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7102

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7103

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7207

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7214

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7322

if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420 && mode_lib->ms.cache_display_cfg.timing.Interlace[k] == 1 && mode_lib->ms.ip.ptoi_supported == true)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7375

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7376

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7449

if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 4 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7455

if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 2 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7461

if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7479

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7480

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7484

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7549

CalculateSwathAndDETConfiguration_params->HActive = mode_lib->ms.cache_display_cfg.timing.HActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7588

mode_lib->ms.cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7647

s->SurfParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7660

s->SurfParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7661

s->SurfParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7802

(dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7831

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7856

mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / mode_lib->ms.RequiredDISPCLK[j];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7871

mode_lib->ms.cache_display_cfg.timing.HTotal[m]) / mode_lib->ms.RequiredDISPCLK[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7889

&mode_lib->ms.cache_display_cfg.timing,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7945

if (mode_lib->ms.cache_display_cfg.timing.RefreshRate[k] > 120)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7956

UseMinimumDCFCLK_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7979

UseMinimumDCFCLK_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7980

UseMinimumDCFCLK_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7983

UseMinimumDCFCLK_params->Interlace = mode_lib->ms.cache_display_cfg.timing.Interlace;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7999

UseMinimumDCFCLK_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8000

UseMinimumDCFCLK_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8347

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8354

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8366

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8391

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8471

mode_lib->ms.cache_display_cfg.timing.HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8486

locals->ReadBandwidthSurfaceLuma[k] = locals->SwathWidthSingleDPPY[k] * locals->BytePerPixelY[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8487

locals->ReadBandwidthSurfaceChroma[k] = locals->SwathWidthSingleDPPC[k] * locals->BytePerPixelC[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8534

CalculateSwathAndDETConfiguration_params->HActive = mode_lib->ms.cache_display_cfg.timing.HActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8571

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8610

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8611

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8615

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8659

s->SurfaceParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8672

s->SurfaceParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8673

s->SurfaceParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8838

mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8856

mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8881

mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8900

((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8910

&mode_lib->ms.cache_display_cfg.timing,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8956

mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8965

myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8974

myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8976

myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8977

myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8978

myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9069

mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9086

locals->cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * locals->VRatioPrefetchY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9265

mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9424

CalculateWatermarks_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9445

CalculateWatermarks_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9446

CalculateWatermarks_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9447

CalculateWatermarks_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9448

CalculateWatermarks_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9485

locals->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9486

mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackDRAMClockChangeWatermark);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9487

locals->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9488

mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackFCLKChangeWatermark);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9508

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9540

mode_lib->ms.cache_display_cfg.timing.HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9546

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9592

mode_lib->ms.cache_display_cfg.timing.HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9597

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9669

s->Tvstartup_margin = (s->MaxVStartupLines[k] - locals->VStartupMin[k]) * mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9687

isInterlaceTiming = (mode_lib->ms.cache_display_cfg.timing.Interlace[k] && !mode_lib->ms.ip.ptoi_supported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9692

s->dlg_vblank_start = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9693

mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9694

s->LSetup = dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9695

s->blank_lines_remaining = (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k]) - locals->VStartup[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9705

s->old_MIN_DST_Y_NEXT_START = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9706

mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9707

+ dml_max(1.0, dml_ceil((dml_float_t) locals->WritebackDelay[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0))

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9708

+ dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9710

if (((locals->VUpdateOffsetPix[k] + locals->VUpdateWidthPix[k] + locals->VReadyOffsetPix[k]) / (double) mode_lib->ms.cache_display_cfg.timing.HTotal[k]) <=

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9712

dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]) / 2.0, 1.0) :

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9713

(int) (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]))) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9724

dml_print("DML::%s: k=%u, HTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.HTotal[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9725

dml_print("DML::%s: k=%u, VTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VTotal[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9726

dml_print("DML::%s: k=%u, VActive = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VActive[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9727

dml_print("DML::%s: k=%u, VFrontPorch = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9741

(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9744

(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9788

CalculateStutterEfficiency_params->Interlace = mode_lib->ms.cache_display_cfg.timing.Interlace;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9801

CalculateStutterEfficiency_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9802

CalculateStutterEfficiency_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9803

CalculateStutterEfficiency_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9812

CalculateStutterEfficiency_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9860

mode_lib->ms.cache_display_cfg.timing.Interlace,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9873

mode_lib->ms.cache_display_cfg.timing.HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9874

mode_lib->ms.cache_display_cfg.timing.VTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9875

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9884

mode_lib->ms.cache_display_cfg.timing.VActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

680

struct dml_timing_cfg_st timing;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

527

void dml_print_dml_display_cfg_timing(const struct dml_timing_cfg_st *timing, dml_uint_t num_plane)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

530

dml_print("DML: timing_cfg: plane=%d, HTotal = %d\n", i, timing->HTotal[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

531

dml_print("DML: timing_cfg: plane=%d, VTotal = %d\n", i, timing->VTotal[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

532

dml_print("DML: timing_cfg: plane=%d, HActive = %d\n", i, timing->HActive[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

533

dml_print("DML: timing_cfg: plane=%d, VActive = %d\n", i, timing->VActive[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

534

dml_print("DML: timing_cfg: plane=%d, VFrontPorch = %d\n", i, timing->VFrontPorch[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

535

dml_print("DML: timing_cfg: plane=%d, VBlankNom = %d\n", i, timing->VBlankNom[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

536

dml_print("DML: timing_cfg: plane=%d, RefreshRate = %d\n", i, timing->RefreshRate[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

537

dml_print("DML: timing_cfg: plane=%d, PixelClock = %f\n", i, timing->PixelClock[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

538

dml_print("DML: timing_cfg: plane=%d, Interlace = %d\n", i, timing->Interlace[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

539

dml_print("DML: timing_cfg: plane=%d, DRRDisplay = %d\n", i, timing->DRRDisplay[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

61

__DML_DLL_EXPORT__ void dml_print_dml_display_cfg_timing(const struct dml_timing_cfg_st *timing, dml_uint_t num_plane);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

100

if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

101

timing->pixel_clock_khz *= 2;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

102

timing->h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

103

timing->v_total = stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

104

timing->h_sync_width = stream->timing.h_sync_width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

105

timing->interlaced = stream->timing.flags.INTERLACE;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

107

hblank_start = stream->timing.h_total - stream->timing.h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

109

timing->h_blank_end = hblank_start - stream->timing.h_addressable - pipe_ctx->dsc_padding_params.dsc_hactive_padding

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

110

- stream->timing.h_border_left - stream->timing.h_border_right;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

112

if (hblank_start < stream->timing.h_addressable)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

113

timing->h_blank_end = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

115

vblank_start = stream->timing.v_total - stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

117

timing->v_blank_end = vblank_start - stream->timing.v_addressable

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

118

- stream->timing.v_border_top - stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

120

timing->drr_config.enabled = stream->ignore_msa_timing_param;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

121

timing->drr_config.drr_active_variable = stream->vrr_active_variable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

122

timing->drr_config.drr_active_fixed = stream->vrr_active_fixed;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

123

timing->drr_config.disallowed = !stream->allow_freesync;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

126

min_hardware_refresh_in_uhz = stream->timing.min_refresh_in_uhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

131

pix_clk_100hz = stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

134

(timing->h_total * (long long)calc_max_hardware_v_total(stream)));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

137

timing->drr_config.min_refresh_uhz = max(stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

141

timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase(stream, false);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

143

timing->drr_config.max_instant_vtotal_delta = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

145

if (stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

146

timing->dsc.enable = dml2_dsc_enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

147

timing->dsc.overrides.num_slices = stream->timing.dsc_cfg.num_slices_h;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

148

timing->dsc.dsc_compressed_bpp_x16 = stream->timing.dsc_cfg.bits_per_pixel;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

150

timing->dsc.enable = dml2_dsc_disable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

152

switch (stream->timing.display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

154

timing->bpc = 6;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

157

timing->bpc = 8;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

160

timing->bpc = 10;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

163

timing->bpc = 12;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

166

timing->bpc = 14;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

169

timing->bpc = 16;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

172

timing->bpc = 9;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

175

timing->bpc = 11;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

178

timing->bpc = 8;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

182

timing->vblank_nom = timing->v_total - timing->v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

209

switch (stream->timing.pixel_encoding) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

218

if (stream->timing.flags.DSC && !stream->timing.dsc_cfg.ycbcr422_simple)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

370

surface->plane0.width = stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

371

surface->plane0.height = stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

372

surface->plane1.width = stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

373

surface->plane1.height = stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

388

if (stream->timing.h_addressable > 3840)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

391

width = stream->timing.h_addressable; // 4K max

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

393

if (stream->timing.v_addressable > 2160)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

396

height = stream->timing.v_addressable; // 4K max

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

640

stream->dst.height >= stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

754

populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index], dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

79

max_hw_v_total -= stream->timing.v_front_porch + 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

85

static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

93

timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

94

timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

95

timing->h_front_porch = stream->timing.h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

96

timing->v_front_porch = stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

97

timing->pixel_clock_khz = stream->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

99

timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

255

memcpy(&phantom_stream->timing, &main_stream->timing, sizeof(phantom_stream->timing));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

260

phantom_stream->timing.v_front_porch = phantom_stream_descriptor->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

261

phantom_stream->timing.v_addressable = phantom_stream_descriptor->timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

262

phantom_stream->timing.v_total = phantom_stream_descriptor->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

263

phantom_stream->timing.flags.DSC = 0; // phantom always has DSC disabled

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

266

phantom_stream->dst.height = stream_programming->phantom_stream.descriptor.timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

269

phantom_stream->src.height = (double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

407

struct dml2_timing_cfg timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

160

phantom->timing.v_total = meta->v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

161

phantom->timing.v_active = meta->v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

162

phantom->timing.v_front_porch = meta->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

163

phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

164

phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

165

phantom->timing.drr_config.enabled = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

177

(double)main->composition.scaler_info.plane0.v_ratio * (double)phantom_stream->timing.v_active, 16.0),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

180

(double)main->composition.scaler_info.plane1.v_ratio * (double)phantom_stream->timing.v_active, 16.0),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10002

line_time = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10169

l->DETBufferingTimeY = l->LinesInDETYRoundedDownToSwath * ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10183

bool isInterlaceTiming = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !p->ProgressiveToInterlaceUnitInOPP;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10187

l->FrameTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total / 2.0, 1.0) : p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total) * (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10188

l->VActiveTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_active / 2.0, 1.0) : p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_active) * (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10259

SinglePixelClock = ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10260

SingleHTotal = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10261

SingleVTotal = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10262

} else if (SinglePixelClock != ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10263

SingleHTotal != p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10264

SingleVTotal != p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10499

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10565

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10566

mode_lib->mp.vactive_sw_bw_l[k] = mode_lib->mp.SwathWidthSingleDPPY[k] * mode_lib->mp.BytePerPixelY[k] / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10567

mode_lib->mp.vactive_sw_bw_c[k] = mode_lib->mp.SwathWidthSingleDPPC[k] * mode_lib->mp.BytePerPixelC[k] / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10635

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10636

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10640

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10670

s->SurfaceParameters[k].PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10683

s->SurfaceParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10684

s->SurfaceParameters[k].HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10964

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) / mode_lib->mp.Dispclk;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1104

l->TotalPixelRate += display_cfg->stream_descriptors[k].timing.pixel_clock_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11049

s->line_times[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11050

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1109

l->DETBudgetPerStream[k] = (unsigned int)((double) display_cfg->stream_descriptors[k].timing.pixel_clock_khz * MaxTotalDETInKByte / l->TotalPixelRate);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11120

&display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11180

!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11185

myPipe->PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11199

myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11201

myPipe->VBlank = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11202

myPipe->HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11203

myPipe->HActive = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11351

double line_time_us = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11352

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11508

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11719

mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k] = math_max2(0, mode_lib->mp.VStartupMin[k] * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11720

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib->mp.Watermark.WritebackDRAMClockChangeWatermark);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11721

mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k] = math_max2(0, mode_lib->mp.VStartupMin[k] * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11722

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib->mp.Watermark.WritebackFCLKChangeWatermark);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11732

DML_LOG_VERBOSE("DML::%s: DEBUG PixelClock = %ld kHz\n", __func__, (display_cfg->stream_descriptors[display_cfg->plane_descriptors[0].stream_index].timing.pixel_clock_khz));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11846

s->Tvstartup_margin = (s->MaxVStartupLines[k] - mode_lib->mp.VStartupMin[k]) * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11860

isInterlaceTiming = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !mode_lib->ip.ptoi_supported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11865

s->dlg_vblank_start = ((isInterlaceTiming ? math_floor2((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch) / 2.0, 1.0) :

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11866

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total) - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11867

s->LSetup = math_floor2(4.0 * mode_lib->mp.TSetup[k] / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)), 1.0) / 4.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11868

s->blank_lines_remaining = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active) - mode_lib->mp.VStartup[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11878

if (((mode_lib->mp.VUpdateOffsetPix[k] + mode_lib->mp.VUpdateWidthPix[k] + mode_lib->mp.VReadyOffsetPix[k]) / (double) display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) <=

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11880

math_floor2((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib->mp.VStartup[k]) / 2.0, 1.0) :

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11881

(int)(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib->mp.VStartup[k]))) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11892

DML_LOG_VERBOSE("DML::%s: k=%u, HTotal = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11893

DML_LOG_VERBOSE("DML::%s: k=%u, VTotal = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11894

DML_LOG_VERBOSE("DML::%s: k=%u, VActive = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11895

DML_LOG_VERBOSE("DML::%s: k=%u, VFrontPorch = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11909

(display_cfg->stream_descriptors[k].timing.h_total * display_cfg->stream_descriptors[k].writeback.writeback_stream[0].input_height

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11910

/ ((double)display_cfg->stream_descriptors[k].timing.pixel_clock_khz / 1000))

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12383

l->timing = &display_cfg->stream_descriptors[display_cfg->plane_descriptors[l->plane_idx].stream_index].timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12389

l->htotal = l->timing->h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12390

l->hactive = l->timing->h_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12391

l->hblank_end = l->timing->h_blank_end;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12392

l->vblank_end = l->timing->v_blank_end;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12393

l->interlaced = l->timing->interlaced;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12394

l->pclk_freq_in_mhz = (double)l->timing->pixel_clock_khz / 1000;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12772

base_programming->htotal = (uint16_t)stream_descriptor->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12773

base_programming->vtotal = (uint16_t)stream_descriptor->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12775

stream_descriptor->timing.v_front_porch);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12777

stream_descriptor->timing.v_front_porch -

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12778

stream_descriptor->timing.v_active);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12779

base_programming->config.bits.is_drr = stream_descriptor->timing.drr_config.enabled;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12788

stream_descriptor->timing.v_front_porch -

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12916

(int)(display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_idx].stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12917

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_idx].stream_index].timing.pixel_clock_khz / 1000) * mode_lib->ms.TWait[plane_idx]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12938

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.pixel_clock_khz / 1000));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12939

phantom_processing_delay_lines = (unsigned int)(phantom_processing_delay_pix / (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12941

display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.h_total,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12953

main_v_blank_lines = display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

160

double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

161

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

177

} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

178

out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

183

DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3519

double pixel_rate_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3661

const struct dml2_timing_cfg *timing,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3667

double line_time_us = (double)timing->h_total / ((double)timing->pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3668

unsigned int vblank_actual = timing->v_total - timing->v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3670

unsigned int vblank_avail = (timing->vblank_nom == 0) ? vblank_nom_default_in_line : (unsigned int)timing->vblank_nom;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3674

if (timing->interlaced && !ptoi_supported)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3679

DML_LOG_VERBOSE("DML::%s: VBlankNom = %lu\n", __func__, timing->vblank_nom);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

434

PixelClockBackEnd[k] = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

435

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && ptoi_supported == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6763

double h_total = (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6764

double pixel_clock_mhz = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6775

double h_total = (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6776

double pixel_clock_mhz = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6968

((double)p->display_cfg->stream_descriptors[stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6969

(double)p->display_cfg->stream_descriptors[stream_index].timing.pixel_clock_khz * 1000.0));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7277

(unsigned int)math_ceil(watermarks->DRAMClockChangeWatermark / ((double)stream_descriptor->timing.h_total * 1000.0 / (double)stream_descriptor->timing.pixel_clock_khz));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7279

if (pstate_keepout_dst_lines[i] > stream_descriptor->timing.v_total - 1) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7280

pstate_keepout_dst_lines[i] = stream_descriptor->timing.v_total - 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7389

s->line_times[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7412

!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7417

myPipe->PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7431

myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7433

myPipe->VBlank = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7434

myPipe->HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7435

myPipe->HActive = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7777

(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8078

mode_lib->ms.vactive_sw_bw_l[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelY[k], 1.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8079

mode_lib->ms.vactive_sw_bw_c[k] = mode_lib->ms.SwathWidthCSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelC[k], 2.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8082

display_cfg->plane_descriptors[k].cursor.cursor_bpp / 8.0 / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8085

DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthLuma = %f\n", __func__, k, mode_lib->ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8086

DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthChroma = %f\n", __func__, k, mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * math_ceil2(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio / 2.0);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8098

* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8099

/ ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 8.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8104

* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8105

/ ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 4.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8150

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8365

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8366

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8368

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8369

mode_lib->ms.support.NumberOfDSCSlices[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8389

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8397

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8408

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8416

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8433

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8434

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8443

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8481

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8491

DML_LOG_VERBOSE("DML::%s: k=%d num_slices = %d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8567

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8574

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8655

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_420 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && mode_lib->ip.ptoi_supported == true)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8658

if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 && !mode_lib->ip.dsc422_native_support)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8712

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8713

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

878

SwathWidthY[k] = (unsigned int)(math_min2((double)SwathWidthSingleDPPY[k], math_round((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active / odm_hactive_factor * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio)));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8790

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active > s->NumDSCUnitRequired * (unsigned int)mode_lib->ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8811

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8812

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8816

((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

886

DML_LOG_VERBOSE("DML::%s: k=%u HActive=%lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8882

s->SurfParameters[k].PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8895

s->SurfParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8896

s->SurfParameters[k].HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9080

double line_time_us = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9166

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) / mode_lib->ms.RequiredDISPCLK;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9174

bool isInterlaceTiming = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !mode_lib->ip.ptoi_supported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9178

&display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9219

unsigned long long refresh_rate = (unsigned long long) ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz * 1000 /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9220

(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9221

(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9636

double pixel_clock_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9766

p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9767

(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9768

p->TimePerMetaChunkVBlank[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9769

(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9770

p->TimePerMetaChunkFlip[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9771

(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9791

p->TimePerChromaMetaChunkNominal[k] = p->meta_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9792

p->TimePerChromaMetaChunkVBlank[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9793

p->TimePerChromaMetaChunkFlip[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9826

pixel_clock_mhz = ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9829

p->time_per_tdlut_group[k] = 2 * p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / p->tdlut_groups_per_2row_ub[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9858

p->time_per_pte_group_nom_luma[k] = p->DST_Y_PER_PTE_ROW_NOM_L[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9859

p->time_per_pte_group_vblank_luma[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9860

p->time_per_pte_group_flip_luma[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9884

p->time_per_pte_group_nom_chroma[k] = p->DST_Y_PER_PTE_ROW_NOM_C[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9885

p->time_per_pte_group_vblank_chroma[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9886

p->time_per_pte_group_flip_chroma[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9946

double pixel_clock_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1577

const struct dml2_timing_cfg *timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

338

double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

339

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

355

} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

356

out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

362

DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

579

phantom->timing.v_total = meta->v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

580

phantom->timing.v_active = meta->v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

581

phantom->timing.v_front_porch = meta->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

582

phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

583

phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

584

phantom->timing.drr_config.enabled = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

596

(double)main->composition.scaler_info.plane0.v_ratio * (double)phantom_stream->timing.v_active, 16.0),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

599

(double)main->composition.scaler_info.plane1.v_ratio * (double)phantom_stream->timing.v_active, 16.0),

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

436

if (memcmp(&display_config->stream_descriptors[remap_array[i - 1]].timing, &display_config->stream_descriptors[remap_array[i]].timing, sizeof(struct dml2_timing_cfg))) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

444

if (display_config->stream_descriptors[remap_array[i]].timing.drr_config.enabled) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

217

if (memcmp(&display_config->display_config.stream_descriptors[remap_array[i - 1]].timing,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

218

&display_config->display_config.stream_descriptors[remap_array[i]].timing,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

226

if (display_config->display_config.stream_descriptors[remap_array[i]].timing.drr_config.enabled) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

250

static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

257

unsigned long h_blank_start = timing->h_total - timing->h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

259

return (timing->h_total % denominator == 0) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

261

(timing->h_blank_end % denominator == 0) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

262

(timing->h_sync_width % denominator == 0);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

319

else if (!is_h_timing_divisible_by(&display_config->stream_descriptors[i].timing, 2))

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

352

odm_load = display_config->stream_descriptors[i].timing.pixel_clock_khz

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

410

if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

429

if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1051

if (!stream_descriptor->timing.drr_config.enabled)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1066

if (stream_descriptor->timing.drr_config.max_instant_vtotal_delta > 0 &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1067

stream_fams2_meta->method_drr.stretched_vtotal - stream_fams2_meta->nom_vtotal > stream_descriptor->timing.drr_config.max_instant_vtotal_delta) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1136

if (stream_descriptor->timing.interlaced) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1143

if (microschedule_vlines >= stream_descriptor->timing.v_active ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1526

stream_descriptor->timing.drr_config.enabled &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1527

(stream_descriptor->timing.drr_config.drr_active_fixed || stream_descriptor->timing.drr_config.drr_active_variable)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1532

stream_descriptor->timing.drr_config.enabled &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1533

stream_descriptor->timing.drr_config.drr_active_variable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1538

stream_descriptor->timing.drr_config.enabled &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1539

stream_descriptor->timing.drr_config.drr_active_variable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1544

!stream_descriptor->timing.drr_config.enabled ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1545

stream_descriptor->timing.drr_config.disallowed)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1550

(!stream_descriptor->timing.drr_config.enabled ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1551

(!stream_descriptor->timing.drr_config.drr_active_fixed && !stream_descriptor->timing.drr_config.drr_active_variable)) ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1553

stream_descriptor->timing.drr_config.enabled &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1554

stream_descriptor->timing.drr_config.drr_active_variable))) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1671

const struct dml2_timing_cfg *timing = &stream_descriptor->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1681

stream_fams2_meta->otg_vline_time_us = (double)timing->h_total / timing->pixel_clock_khz * 1000.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1682

stream_fams2_meta->nom_vtotal = stream_descriptor->timing.vblank_nom + stream_descriptor->timing.v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1683

stream_fams2_meta->nom_refresh_rate_hz = timing->pixel_clock_khz * 1000.0 /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1684

(stream_fams2_meta->nom_vtotal * timing->h_total);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1687

stream_fams2_meta->vblank_start = timing->v_blank_end + timing->v_active;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1689

if (stream_descriptor->timing.drr_config.enabled == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1690

if (stream_descriptor->timing.drr_config.min_refresh_uhz != 0.0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1691

stream_fams2_meta->max_vtotal = (unsigned int)math_floor((double)stream_descriptor->timing.pixel_clock_khz /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1692

((double)stream_descriptor->timing.drr_config.min_refresh_uhz * stream_descriptor->timing.h_total) * 1e9);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1695

stream_fams2_meta->max_vtotal = (unsigned int)math_floor((double)stream_descriptor->timing.pixel_clock_khz /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1696

(48000000.0 * stream_descriptor->timing.h_total) * 1e9);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1701

stream_fams2_meta->min_refresh_rate_hz = timing->pixel_clock_khz * 1000.0 /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1702

(stream_fams2_meta->max_vtotal * timing->h_total);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1729

timing->v_active - math_max2(1.0, stream_fams2_meta->min_allow_width_otg_vlines) - stream_fams2_meta->dram_clk_change_blackout_otg_vlines));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1739

timing->v_blank_end + stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1778

stream_descriptor->timing.v_blank_end +

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2287

line_time_us = (double)in_out->base_display_config->display_config.stream_descriptors[i].timing.h_total / (in_out->base_display_config->display_config.stream_descriptors[i].timing.pixel_clock_khz * 1000) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2288

vblank_nom_time_us = line_time_us * in_out->base_display_config->display_config.stream_descriptors[i].timing.vblank_nom;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

711

static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

718

unsigned long h_blank_start = timing->h_total - timing->h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

720

return (timing->h_total % denominator == 0) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

722

(timing->h_blank_end % denominator == 0) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

723

(timing->h_sync_width % denominator == 0);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

782

else if (!is_h_timing_divisible_by(&display_config->stream_descriptors[i].timing, 2))

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

817

odm_load = display_config->stream_descriptors[i].timing.pixel_clock_khz

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

875

if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

894

if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

953

master_timing = &display_config->display_config.stream_descriptors[i].timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

978

&display_config->display_config.stream_descriptors[j].timing,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

547

temp = (unsigned int)math_ceil(plane->composition.scaler_info.plane0.h_ratio * stream->timing.h_active / odm_combine_factor);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

553

temp = (unsigned int)math_ceil(plane->composition.scaler_info.plane1.h_ratio * stream->timing.h_active / odm_combine_factor);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

593

stream->timing.h_active, num_dpps, scaling_transform,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

604

stream->timing.h_active, num_dpps, scaling_transform,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

246

refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

247

pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

248

/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

266

unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

267

(double)(stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

377

microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

378

phantom->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

381

time_us = (microschedule_lines * phantom->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

382

(double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

396

vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

397

(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

398

vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

399

(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

400

vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

401

subvp_pipes[0]->stream->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

402

(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

403

vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

404

subvp_pipes[1]->stream->timing.h_total) /

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

405

(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

462

main_timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

463

phantom_timing = &phantom_stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

554

schedulable = dml2_svp_drr_schedulable(ctx, context, &context->res_ctx.pipe_ctx[vblank_index].stream->timing);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

557

main_timing = &subvp_pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

558

phantom_timing = &phantom_stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

559

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

677

(ref_pipe->stream->timing.pix_clk_100hz * 100) /

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

678

(double)ref_pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

687

phantom_stream->timing.v_front_porch = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

689

line_time = phantom_stream->timing.h_total / ((double)phantom_stream->timing.pix_clk_100hz * 100);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

690

fp_and_sync_width_time = (phantom_stream->timing.v_front_porch + phantom_stream->timing.v_sync_width) * line_time;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

70

mall_alloc_height_blk_aligned = (pipe->stream->timing.v_addressable - 1 + mblk_height - 1) /

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

704

phantom_stream->timing.v_addressable = phantom_vactive;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

706

phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

707

phantom_stream->timing.v_front_porch +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

708

phantom_stream->timing.v_sync_width +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

710

phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

722

memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

773

phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1009

if (in->timing.h_addressable > 3840)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1012

width = in->timing.h_addressable; // 4K max

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1014

if (in->timing.v_addressable > 2160)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1017

height = in->timing.v_addressable; // 4K max

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1333

populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1398

populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_plane_location, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

756

out->HActive[location] = in->timing.h_addressable + in->timing.h_border_left + in->timing.h_border_right;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

757

out->VActive[location] = in->timing.v_addressable + in->timing.v_border_bottom + in->timing.v_border_top;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

758

out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) / in->timing.h_total) / in->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

759

out->VFrontPorch[location] = in->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

760

out->PixelClock[location] = in->timing.pix_clk_100hz / 10000.00;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

761

if (in->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

763

out->HTotal[location] = in->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

764

out->VTotal[location] = in->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

765

out->Interlace[location] = in->timing.flags.INTERLACE;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

766

hblank_start = in->timing.h_total - in->timing.h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

768

- in->timing.h_addressable

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

769

- in->timing.h_border_left

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

770

- in->timing.h_border_right;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

771

vblank_start = in->timing.v_total - in->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

773

- in->timing.v_addressable

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

774

- in->timing.v_border_top

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

775

- in->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

784

out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

787

out->DSCSlices[location] = in->timing.dsc_cfg.num_slices_h;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

808

switch (in->timing.display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

838

switch (in->timing.pixel_encoding) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

849

if (in->timing.flags.DSC && !in->timing.dsc_cfg.ycbcr422_simple)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

861

if (in->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

862

out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

884

out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

894

out->SurfaceWidthY[location] = in->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

895

out->SurfaceHeightY[location] = in->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

896

out->SurfaceWidthC[location] = in->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

897

out->SurfaceHeightC[location] = in->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

243

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

245

hactive = timing->h_addressable + timing->h_border_left + timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

246

vactive = timing->v_addressable + timing->v_border_bottom + timing->v_border_top;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

247

hblank_start = pipe_ctx->stream->timing.h_total - pipe_ctx->stream->timing.h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

248

vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

250

hblank_end = hblank_start - timing->h_addressable - timing->h_border_left - timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

251

vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

262

pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

263

pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

268

pipe_ctx->pipe_dlg_param.vfront_porch = pipe_ctx->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

269

pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

270

pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

553

(stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

555

stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

204

struct dml_timing_cfg_st *timing = &mode_lib->ms.cache_display_cfg.timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

211

dml_uint_t htotal = timing->HTotal[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

212

dml_uint_t hactive = timing->HActive[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

213

dml_uint_t hblank_end = timing->HBlankEnd[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

214

dml_uint_t vblank_end = timing->VBlankEnd[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

215

dml_bool_t interlaced = timing->Interlace[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

216

dml_float_t pclk_freq_in_mhz = (dml_float_t) timing->PixelClock[plane_idx];

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

100

if (timing->flags.DSC)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

101

return dc_dsc_stream_bandwidth_in_kbps(timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

102

timing->dsc_cfg.bits_per_pixel,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

103

timing->dsc_cfg.num_slices_h,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

104

timing->dsc_cfg.is_dp);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1049

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

106

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1070

dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy, link_encoding);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1071

pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1072

pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1081

is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1091

switch (timing->pixel_encoding) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1122

if (branch_max_throughput_mps && dsc_div_by_10_round_up(timing->pix_clk_100hz) > branch_max_throughput_mps * 1000)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1129

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1169

int pix_clk_per_slice_khz = dsc_div_by_10_round_up(timing->pix_clk_100hz) / min_slices_h;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1249

(timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0)))

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1252

if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) // For the case when pic_height < dsc_policy.min_sice_height

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1271

timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1298

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1305

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1307

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

131

kbps = timing->pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1312

timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1320

uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1328

timing, num_slices_h, is_dp);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1330

actual_bandwidth_in_kbps = dc_fixpt_from_fraction(timing->pix_clk_100hz, 10);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1337

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

134

if (timing->flags.Y_ONLY != 1) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1348

refresh_rate = dc_fixpt_from_int(timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1349

refresh_rate = dc_fixpt_div_int(refresh_rate, timing->h_total);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1350

refresh_rate = dc_fixpt_div_int(refresh_rate, timing->v_total);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1354

max_dsc_overhead = dc_fixpt_mul_int(max_dsc_overhead, timing->v_total);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1362

void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

137

if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1388

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

139

else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1401

switch (timing->pixel_encoding) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

144

kbps = apply_128b_132b_stream_overhead(timing, kbps);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

147

timing->vic == 0 && timing->hdmi_vic == 0 &&

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

148

timing->frl_uncompressed_video_bandwidth_in_kbps != 0)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

149

kbps = timing->frl_uncompressed_video_bandwidth_in_kbps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

158

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

165

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

171

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

191

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

464

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

479

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

481

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

484

timing->pixel_encoding, &dsc_common_caps);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

487

is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

492

config.num_slices_h, &dsc_common_caps, timing, link_encoding, range);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

498

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

502

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

62

const struct dc_crtc_timing *timing, const uint32_t kbps)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

638

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

661

dc_fixpt_div_int(dc_fixpt_from_int(dsc_div_by_10_round_up(timing->pix_clk_100hz)),

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

663

dc_fixpt_div_int(dc_fixpt_from_int(timing->h_addressable + timing->h_border_left + timing->h_border_right),

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

69

if (!timing->flags.DSC) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

74

bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

770

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

780

timing, num_slices_h, is_dp);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

785

bpp_x16 = dc_fixpt_div_int(bpp_x16, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

79

overhead_factor = dc_fixpt_from_int(timing->h_addressable);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

802

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

806

uint32_t preferred_bpp_x16 = timing->dsc_fixed_bits_per_pixel_x16;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

833

range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing, link_encoding);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

836

range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

840

range->min_kbps = dc_dsc_stream_bandwidth_in_kbps(timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

858

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

868

num_slices_h, dsc_common_caps, timing, link_encoding, &range)) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

879

target_bandwidth_kbps, timing, num_slices_h,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

94

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1101

hubp->cur_rect.w = param->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1102

hubp->cur_rect.h = param->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

186

struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

192

unsigned int htotal = timing->h_total;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

207

vblank_start = timing->v_total - timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

208

vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

350

struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

355

hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

265

struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

362

struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1185

dto_params.timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1210

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1329

struct dc_crtc_timing *crtc_timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1398

stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1405

stream->timing.h_addressable

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1406

+ stream->timing.h_border_left

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1407

+ stream->timing.h_border_right;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1410

stream->timing.v_addressable

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1411

+ stream->timing.v_border_top

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1412

+ stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1417

stream->timing.flags.INTERLACE;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1420

(stream->timing.pix_clk_100hz*100)/

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1421

(stream->timing.h_total*stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1424

stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1433

stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1436

stream->timing.dsc_cfg.bits_per_pixel;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1439

stream->timing.dsc_cfg.num_slices_h;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1444

(stream->timing.pix_clk_100hz)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1504

if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1560

&stream->timing,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1633

stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1640

stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1691

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1949

edp_stream->sink, &edp_stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2040

(stream->timing.h_total * 10) /

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2041

stream->timing.pix_clk_100hz +

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2276

params.source_view_width = pipe_ctx->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2277

params.source_view_height = pipe_ctx->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2563

pipe_ctx->stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3049

pipe_ctx->stream->timing.h_total,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3050

pipe_ctx->stream->timing.v_total,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3051

pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3125

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3307

pipes[i].stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

667

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

681

timing->h_addressable

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

682

+ timing->h_border_left

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

683

+ timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

126

params.source_view_width = pipe_ctx->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

127

params.source_view_height = pipe_ctx->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

155

pipe_ctx->stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

257

if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

404

pipe_ctx->stream->timing.h_total,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

405

pipe_ctx->stream->timing.v_total,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

406

pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1220

&stream->timing,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1249

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

141

lines_to_vupdate = stream->timing.v_total - vpos + vupdate_start;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

146

stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

150

vupdate_end += stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

152

if (lines_to_vupdate > stream->timing.v_total - vupdate_end + vupdate_start)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1985

(pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1987

pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2214

lines_to_vupdate = stream->timing.v_total - vpos + vupdate_start;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2219

stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2224

vupdate_end += stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2227

if (lines_to_vupdate > stream->timing.v_total - vupdate_end + vupdate_start)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2356

pipe->stream->timing.pix_clk_100hz * 100 /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2357

pipe->stream->timing.h_total /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2358

pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2460

grouped_pipes[i]->stream->timing.pix_clk_100hz =

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2519

grouped_pipes[master]->stream->timing.pix_clk_100hz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2520

grouped_pipes[i]->stream->timing.pix_clk_100hz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3158

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3220

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3320

if (context->streams[i]->timing.timing_3d_format

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3479

stream->timing.timing_3d_format;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3508

stream->timing.flags.RIGHT_EYE_3D_POLARITY;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3523

if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3533

&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3537

&stream->timing,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3649

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3907

struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3909

if (timing->flags.INTERLACE == 1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3910

if (timing->v_front_porch < 2)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3911

timing->v_front_porch = 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3913

if (timing->v_front_porch < 1)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3914

timing->v_front_porch = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3920

const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3950

const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3954

*start_line = vupdate_pos - ((vupdate_pos / timing->v_total) * timing->v_total);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3956

*start_line = vupdate_pos + ((-vupdate_pos / timing->v_total) + 1) * timing->v_total - 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3957

*end_line = (*start_line + 2) % timing->v_total;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3966

const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3977

*start_line = vline_pos - ((vline_pos / timing->v_total) * timing->v_total);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3979

*start_line = vline_pos + ((-vline_pos / timing->v_total) + 1) * timing->v_total - 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3980

*end_line = (*start_line + 2) % timing->v_total;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3984

*end_line = (*start_line + 2) % timing->v_total;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4025

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4030

if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4031

params.timing.pix_clk_100hz /= 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1211

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1253

stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1266

stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1711

&pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1921

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2008

pipe_ctx->stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2477

&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2517

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2708

(pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2710

pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2766

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2774

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2785

params.timing.pix_clk_100hz /= 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2864

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2881

dto_params.timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3022

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3043

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3045

dto_params.timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3092

timing->h_addressable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3093

+ timing->h_border_left

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3094

+ timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

786

flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

787

stream->timing.h_border_left -

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

788

stream->timing.h_border_right;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

842

bool interlace = stream->timing.flags.INTERLACE;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

847

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

904

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

906

dto_params.timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

924

&stream->timing,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

954

stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

966

udelay(stream->timing.v_total * (stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz));

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

600

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

606

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing))

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

607

params.timing.pix_clk_100hz /= 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

64

(pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

66

pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

976

stream->adjust.v_total_max : stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

977

unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

978

100LL, (v_total * stream->timing.h_total));

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

548

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

583

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

103

dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

104

dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

105

dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

106

dsc_cfg.color_depth = stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

108

dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

191

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

212

update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

333

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

341

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1031

stream->timing.pix_clk_100hz > 480000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1057

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1058

stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1059

dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1060

dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1061

dsc_cfg.color_depth = stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1063

dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1148

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1156

pipe_ctx->stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1163

dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1190

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1198

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1318

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1328

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1330

params.timing.pix_clk_100hz /= 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1426

struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1428

unsigned int frame_rate = timing->pix_clk_100hz / (timing->h_total * timing->v_total);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1476

struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1478

if (timing)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1479

params.vertical_blank_start = timing->v_total - timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1502

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1513

pix_clk_mhz = timing->pix_clk_100hz / 10000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

359

dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

360

dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

361

dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

362

dsc_cfg.color_depth = stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

364

dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

447

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

468

update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1079

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1471

&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1550

otg_master->stream->timing.flags.DSC);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1585

&otg_master->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1593

opp_heads[i]->stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1618

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1864

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1976

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2062

pipe_ctx->stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2432

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2446

&pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

704

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

769

struct dc_crtc_timing patched_crtc_timing = stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

848

stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

918

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

935

timing->h_addressable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

936

+ timing->h_border_left

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

937

+ timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

86

const struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

168

struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

331

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

159

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

195

bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

79

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

100

struct dc_crtc_timing timing;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

200

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

202

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

274

bool enable, const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

296

const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

313

bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

143

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

487

stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

122

stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

127

&stream->timing,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

134

&stream->timing,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

140

&stream->timing,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

145

&stream->timing);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

101

stream->timing.flags.DSC,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

52

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

61

timing->h_total - timing->h_addressable),

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

62

dc_fixpt_from_fraction(timing->pix_clk_100hz, 10));

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

98

&stream->timing,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1015

if (!pipe_ctx->stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1038

if (!pipe_ctx->stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1167

kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1539

dc_bandwidth_in_kbps_from_timing(&stream->timing,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1971

bool is_vga_mode = (stream->timing.h_addressable == 640)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1972

&& (stream->timing.v_addressable == 480);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1977

stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2009

stream->timing.flags.LTE_340MCSC_SCRAMBLE);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2014

display_color_depth = stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2015

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2173

stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2329

int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2434

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2543

!pipe_ctx->stream->timing.flags.DSC &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2576

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2627

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

823

stream->timing.pix_clk_100hz > 480000;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

835

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

836

stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

837

dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

838

dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

839

dsc_cfg.color_depth = stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

841

dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

951

if (!pipe_ctx->stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

967

dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

968

dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

969

dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

970

dsc_cfg.color_depth = stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

972

dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

sys/dev/pci/drm/amd/display/dc/link/link_hwss_hpo_frl.c

42

&stream->timing,

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

123

switch (timing->timing_3d_format) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

134

struct dc_crtc_timing outputTiming = *timing;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

136

if (timing->flags.DSC && !timing->dsc_cfg.is_frl)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

143

if (get_tmds_output_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

152

if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

155

if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

158

if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

161

if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

164

if (timing->display_color_depth == COLOR_DEPTH_666 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

167

else if (timing->display_color_depth == COLOR_DEPTH_888 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

170

else if (timing->display_color_depth == COLOR_DEPTH_101010 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

173

else if (timing->display_color_depth == COLOR_DEPTH_121212 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

176

else if (timing->display_color_depth == COLOR_DEPTH_161616 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

179

} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

182

if (timing->display_color_depth == COLOR_DEPTH_888 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

185

else if (timing->display_color_depth == COLOR_DEPTH_101010 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

188

else if (timing->display_color_depth == COLOR_DEPTH_121212 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

191

else if (timing->display_color_depth == COLOR_DEPTH_161616 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

194

} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

197

if (timing->display_color_depth == COLOR_DEPTH_888 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

200

else if (timing->display_color_depth == COLOR_DEPTH_101010 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

203

else if (timing->display_color_depth == COLOR_DEPTH_121212 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

206

else if (timing->display_color_depth == COLOR_DEPTH_161616 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

209

} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

212

if (timing->display_color_depth == COLOR_DEPTH_888 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

215

else if (timing->display_color_depth == COLOR_DEPTH_101010 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

218

else if (timing->display_color_depth == COLOR_DEPTH_121212 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

221

else if (timing->display_color_depth == COLOR_DEPTH_161616 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

267

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

270

return dc_bandwidth_in_kbps_from_timing(timing,

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

276

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

284

if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

290

if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

291

timing->h_addressable == (uint32_t) 640 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

292

timing->v_addressable == (uint32_t) 480)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

303

req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link));

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

307

timing->pix_clk_100hz > link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.max_uncompressed_pixel_rate_cap * 10000;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

309

if (is_max_uncompressed_pixel_rate_exceeded && !timing->flags.DSC) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

335

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

347

if (max_pix_clk != 0 && get_tmds_output_pixel_clock_100hz(timing) > max_pix_clk)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

351

if (!dp_active_dongle_validate_timing(timing, dpcd_caps))

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

359

timing))

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

38

static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

41

uint32_t pxl_clk = timing->pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

422

timing_bw = dp_get_timing_bandwidth_kbps(&stream->timing, link);

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

43

if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

45

else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

48

if (timing->display_color_depth == COLOR_DEPTH_101010)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

50

else if (timing->display_color_depth == COLOR_DEPTH_121212)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

555

const struct dc_crtc_timing *timing = audio_params->crtc_timing;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

57

const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

581

timing->pix_clk_100hz, (long long)timing->h_total * 10);

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

66

if (timing->pixel_encoding == PIXEL_ENCODING_RGB)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

77

switch (timing->pixel_encoding) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

98

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.h

32

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

951

uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

972

if (stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

978

struct dc_crtc_timing tmp_timing = stream->timing;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1799

req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, link_encoding);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1043

((stream->timing.h_total * 1000000) /

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1044

(stream->timing.pix_clk_100hz / 10)) + 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

817

psr_context->crtcTimingVerticalTotal = stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

819

timing.pix_clk_100hz * (u64)100),

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

820

stream->timing.v_total),

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

821

stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

843

psr_context->hyst_lines = stream->timing.v_total / 2 / 100;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

326

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

330

uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

331

uint32_t space1_size = timing->v_total - timing->v_addressable;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

333

uint32_t space2_size = timing->v_total - timing->v_addressable;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

351

if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE)

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

185

const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1250

const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1282

const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1285

optc1_enable_stereo(optc, timing, flags);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1612

bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1614

bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1616

two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1617

&& !timing->dsc_cfg.ycbcr422_simple);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

52

static void apply_front_porch_workaround(struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

54

if (timing->flags.INTERLACE == 1) {

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

55

if (timing->v_front_porch < 2)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

56

timing->v_front_porch = 2;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

58

if (timing->v_front_porch < 1)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

59

timing->v_front_porch = 1;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

592

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

599

ASSERT(timing != NULL);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

601

v_blank = (timing->v_total - timing->v_addressable -

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

602

timing->v_border_top - timing->v_border_bottom);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

604

h_blank = (timing->h_total - timing->h_addressable -

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

605

timing->h_border_right -

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

606

timing->h_border_left);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

608

if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

609

timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

610

timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

611

timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

612

timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

613

timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

617

if (timing->flags.INTERLACE == 1)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

625

if (timing->h_total > optc1->max_h_total ||

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

626

timing->v_total > optc1->max_v_total)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

633

if (timing->h_sync_width < optc1->min_h_sync_width ||

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

634

timing->v_sync_width < optc1->min_v_sync_width)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

637

min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

100

timing->v_total > optc1->max_v_total)

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

106

if (timing->h_sync_width < optc1->min_h_sync_width ||

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

107

timing->v_sync_width < optc1->min_v_sync_width)

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

110

min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

70

const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

77

ASSERT(timing != NULL);

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

79

v_blank = (timing->v_total - timing->v_addressable -

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

80

timing->v_border_top - timing->v_border_bottom);

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

82

h_blank = (timing->h_total - timing->h_addressable -

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

83

timing->h_border_right -

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

84

timing->h_border_left);

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

86

if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

87

timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

88

timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

89

timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

90

timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

91

timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

99

if (timing->h_total > optc1->max_h_total ||

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

855

if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1080

if (context->streams[i]->timing.pixel_encoding

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1161

&stream->timing,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1173

&stream->timing);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1176

stream->timing.h_total,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1177

stream->timing.v_total,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1178

stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

892

pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

901

stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

903

pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

905

pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

906

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

909

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

912

if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

926

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

986

context->streams[0]->timing.h_addressable,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

987

context->streams[0]->timing.v_addressable,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

988

context->streams[0]->timing.pix_clk_100hz / 10);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1008

stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1010

pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1012

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1015

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1017

if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1025

stream->clamping.c_depth = stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1026

stream->clamping.pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1039

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

999

pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1230

pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1245

stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1247

pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1249

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1254

else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt == 2)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1261

if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1265

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1278

stream->clamping.c_depth = stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1279

stream->clamping.pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1301

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1443

if (result == DC_OK && dc_stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1523

if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1659

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1662

dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1663

+ stream->timing.h_border_right) / opp_cnt;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1664

dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1665

+ stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1666

dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1667

dsc_cfg.color_depth = stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1669

dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1861

struct dc_crtc_timing timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1866

timing = pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1867

if (timing.h_border_left + timing.h_border_right

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1868

+ timing.v_border_top + timing.v_border_bottom > 0) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1914

(pipe->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1916

pipe->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1928

if (pipe->stream->timing.h_addressable > 7680 &&

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1929

pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1561

if (sec_pipe->stream->timing.flags.DSC == 1) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1887

struct dc_crtc_timing *timing = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1893

timing = &context->streams[0]->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1895

h_v_total = timing->h_total * timing->v_total;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1899

refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1914

struct dc_crtc_timing *timing = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1927

timing = &context->streams[0]->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1928

if (timing == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1931

sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1933

curr_v_blank = timing->v_total - timing->v_addressable;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1935

stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1937

scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1951

min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1656

struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1661

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1675

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1684

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1681

struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1686

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1696

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1705

&context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1709

split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1726

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1758

bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1797

&& pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1625

struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1630

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1640

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1648

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1698

memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1875

struct dc_crtc_timing *timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1923

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1929

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1990

switch (timing->display_color_depth) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2860

if (free_pipe->stream->timing.flags.DSC == 1) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

217

if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

218

pipe->stream->timing.v_addressable != pipe->stream->src.height) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

223

if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

224

pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

265

if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

278

if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

430

struct dc_crtc_timing *timing = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

444

timing = &fpo_candidate_stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

445

if (timing == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

450

sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

452

curr_v_blank = timing->v_total - timing->v_addressable;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

454

stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

456

scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

472

min_refresh_100hz = fpo_candidate_stream->timing.min_refresh_in_uhz / 10000;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

488

struct dc_crtc_timing *timing = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

494

timing = &fpo_candidate_stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

495

if (timing == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

498

h_v_total = timing->h_total * timing->v_total;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

502

refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

595

if (pipe->stream->timing.h_addressable == width &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

596

pipe->stream->timing.v_addressable == height &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

624

if (pipe->stream->timing.v_addressable == 1080 && pipe->stream->timing.h_addressable == 1920)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

665

refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

666

pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

667

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

668

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

726

refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

727

pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

728

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

729

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1700

pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1720

stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1722

pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1724

if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1727

if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1730

stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1740

stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1000

min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1001

(stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1034

in_out_vrr->adjust.v_total_min = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1035

in_out_vrr->adjust.v_total_max = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1086

in_out_vrr->adjust.v_total_min = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1087

in_out_vrr->adjust.v_total_max = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1089

in_out_vrr->adjust.v_total_min = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1090

in_out_vrr->adjust.v_total_max = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1092

in_out_vrr->adjust.v_total_min = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1093

in_out_vrr->adjust.v_total_max = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1122

in_out_vrr->adjust.v_total_min = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1123

in_out_vrr->adjust.v_total_max = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

119

* 10000) * stream->timing.h_total,

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

120

stream->timing.pix_clk_100hz));

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1280

unsigned int total = stream->timing.h_total * stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1283

nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

130

max_hw_v_total -= stream->timing.v_front_porch + 1;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

144

return stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

150

if (refresh_in_uhz <= stream->timing.min_refresh_in_uhz) {

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

156

frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

157

stream->timing.h_total), 1000000);

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

158

} else if (refresh_in_uhz >= stream->timing.max_refresh_in_uhz) {

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

164

frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

165

stream->timing.h_total) + (1000000 - 1), 1000000);

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

168

frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

169

stream->timing.h_total) + 500000, 1000000);

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

173

if (v_total < stream->timing.v_total) {

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

174

ASSERT(v_total < stream->timing.v_total);

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

175

v_total = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

197

h_total_up_scaled = stream->timing.h_total * 10000;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

199

* stream->timing.pix_clk_100hz + (h_total_up_scaled - 1),

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

203

duration_in_us) * (stream->timing.pix_clk_100hz / 10)),

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

204

stream->timing.h_total), 1000);

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

208

if (v_total < stream->timing.v_total) {

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

209

ASSERT(v_total < stream->timing.v_total);

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

210

v_total = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

279

current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

280

stream->timing.h_total), 1000);

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

283

if (v_total < stream->timing.v_total)

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

284

v_total = stream->timing.v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

999

if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

144

if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) {

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

250

switch (stream->timing.timing_3d_format) {

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

343

switch (stream->timing.pixel_encoding) {

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

362

switch (stream->timing.pixel_encoding) {

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

401

switch (stream->timing.display_color_depth) {

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

461

format = stream->timing.timing_3d_format;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

465

if (stream->timing.hdmi_vic != 0

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

466

&& stream->timing.h_total >= 3840

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

467

&& stream->timing.v_total >= 2160

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

506

info_packet->sb[5] = stream->timing.hdmi_vic;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

572

info_packet->sb[1] = (stream->timing.v_total & 0x00FF);

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

573

info_packet->sb[2] = (stream->timing.v_total & 0xFF00) >> 8;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

889

num_vblank_lines = stream->timing.v_total -

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

890

stream->timing.v_addressable -

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

891

stream->timing.v_border_top -

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

892

stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

894

vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10);

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

896

line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

955

!stream->timing.dsc_cfg.num_slices_v)

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

958

pic_height = stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

959

stream->timing.v_border_top + stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

961

if (stream->timing.dsc_cfg.num_slices_v == 0)

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

964

slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;

sys/dev/pci/drm/drm_edid.c

3122

typedef void detailed_cb(const struct detailed_timing *timing, void *closure);

sys/dev/pci/drm/drm_edid.c

3531

const struct detailed_timing *timing)

sys/dev/pci/drm/drm_edid.c

3535

const struct detailed_pixel_timing *pt = &timing->data.pixel_data;

sys/dev/pci/drm/drm_edid.c

3581

mode->clock = le16_to_cpu(timing->pixel_clock) * 10;

sys/dev/pci/drm/drm_edid.c

3689

const struct detailed_timing *timing)

sys/dev/pci/drm/drm_edid.c

3693

const u8 *t = (const u8 *)timing;

sys/dev/pci/drm/drm_edid.c

3737

const struct detailed_timing *timing)

sys/dev/pci/drm/drm_edid.c

3744

if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&

sys/dev/pci/drm/drm_edid.c

3772

const struct detailed_timing *timing)

sys/dev/pci/drm/drm_edid.c

3786

if (!mode_in_range(newmode, drm_edid, timing) ||

sys/dev/pci/drm/drm_edid.c

3801

const struct detailed_timing *timing)

sys/dev/pci/drm/drm_edid.c

3815

if (!mode_in_range(newmode, drm_edid, timing) ||

sys/dev/pci/drm/drm_edid.c

3830

const struct detailed_timing *timing)

sys/dev/pci/drm/drm_edid.c

3845

if (!mode_in_range(newmode, drm_edid, timing) ||

sys/dev/pci/drm/drm_edid.c

3859

do_inferred_modes(const struct detailed_timing *timing, void *c)

sys/dev/pci/drm/drm_edid.c

3862

const struct detailed_non_pixel *data = &timing->data.other_data;

sys/dev/pci/drm/drm_edid.c

3865

if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))

sys/dev/pci/drm/drm_edid.c

3870

timing);

sys/dev/pci/drm/drm_edid.c

3879

timing);

sys/dev/pci/drm/drm_edid.c

3884

timing);

sys/dev/pci/drm/drm_edid.c

3892

timing);

sys/dev/pci/drm/drm_edid.c

3915

drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)

sys/dev/pci/drm/drm_edid.c

3919

const u8 *est = ((const u8 *)timing) + 6;

sys/dev/pci/drm/drm_edid.c

3944

do_established_modes(const struct detailed_timing *timing, void *c)

sys/dev/pci/drm/drm_edid.c

3948

if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))

sys/dev/pci/drm/drm_edid.c

3951

closure->modes += drm_est3_modes(closure->connector, timing);

sys/dev/pci/drm/drm_edid.c

3993

do_standard_modes(const struct detailed_timing *timing, void *c)

sys/dev/pci/drm/drm_edid.c

3996

const struct detailed_non_pixel *data = &timing->data.other_data;

sys/dev/pci/drm/drm_edid.c

4000

if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))

sys/dev/pci/drm/drm_edid.c

4050

const struct detailed_timing *timing)

sys/dev/pci/drm/drm_edid.c

4062

cvt = &(timing->data.other_data.data.cvt[i]);

sys/dev/pci/drm/drm_edid.c

4102

do_cvt_mode(const struct detailed_timing *timing, void *c)

sys/dev/pci/drm/drm_edid.c

4106

if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))

sys/dev/pci/drm/drm_edid.c

4109

closure->modes += drm_cvt_modes(closure->connector, timing);

sys/dev/pci/drm/drm_edid.c

4132

do_detailed_mode(const struct detailed_timing *timing, void *c)

sys/dev/pci/drm/drm_edid.c

4137

if (!is_detailed_timing_descriptor(timing))

sys/dev/pci/drm/drm_edid.c

4141

closure->drm_edid, timing);

sys/dev/pci/drm/drm_edid.c

5546

match_identity(const struct detailed_timing *timing, void *data)

sys/dev/pci/drm/drm_edid.c

5552

const char *desc = timing->data.other_data.data.str.str;

sys/dev/pci/drm/drm_edid.c

5553

unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str);

sys/dev/pci/drm/drm_edid.c

5556

!(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) ||

sys/dev/pci/drm/drm_edid.c

5557

is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING)))

sys/dev/pci/drm/drm_edid.c

5606

monitor_name(const struct detailed_timing *timing, void *data)

sys/dev/pci/drm/drm_edid.c

5610

if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))

sys/dev/pci/drm/drm_edid.c

5613

*res = timing->data.other_data.data.str.str;

sys/dev/pci/drm/drm_edid.c

6513

void get_monitor_range(const struct detailed_timing *timing, void *c)

sys/dev/pci/drm/drm_edid.c

6518

const struct detailed_non_pixel *data = &timing->data.other_data;

sys/dev/pci/drm/drm_edid.c

6522

if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))

sys/dev/pci/drm/drm_modes.c

1229

struct display_timing timing;

sys/dev/pci/drm/drm_modes.c

1233

ret = of_get_display_timing(np, "panel-timing", &timing);

sys/dev/pci/drm/drm_modes.c

1237

videomode_from_timing(&timing, &vm);

sys/dev/pci/sdhc_pci.c

322

sdhc_gl9755_bus_clock_pre(struct sdhc_softc *ssc, int freq, int timing)

sys/dev/pcmcia/pcmcia_cis.c

1080

timing = reg & PCMCIA_TPCE_FS_TIMING;

sys/dev/pcmcia/pcmcia_cis.c

1111

if (timing) {

sys/dev/pcmcia/pcmcia_cis.c

974

u_int power, timing, iospace, irq, memspace, misc;

sys/dev/sdmmc/sdhc.c

686

sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)

sys/dev/sdmmc/sdhc.c

699

hp->sc->sc_bus_clock_pre(hp->sc, freq, timing);

sys/dev/sdmmc/sdhc.c

716

if (timing == SDMMC_TIMING_LEGACY)

sys/dev/sdmmc/sdhc.c

723

switch (timing) {

sys/dev/sdmmc/sdhc.c

765

hp->sc->sc_bus_clock_post(hp->sc, freq, timing);

sys/dev/sdmmc/sdmmc_mem.c

1003

error = sdmmc_chip_bus_clock(sc->sct, sc->sch, speed, timing);

sys/dev/sdmmc/sdmmc_mem.c

1022

if (timing == SDMMC_TIMING_MMC_HS200) {

sys/dev/sdmmc/sdmmc_mem.c

706

int timing = -1;

sys/dev/sdmmc/sdmmc_mem.c

714

timing = SDMMC_TIMING_UHS_SDR50;

sys/dev/sdmmc/sdmmc_mem.c

717

timing = SDMMC_TIMING_UHS_SDR104;

sys/dev/sdmmc/sdmmc_mem.c

725

timing = SDMMC_TIMING_MMC_HS200;

sys/dev/sdmmc/sdmmc_mem.c

733

timing));

sys/dev/sdmmc/sdmmc_mem.c

735

return sdmmc_chip_execute_tuning(sc->sct, sc->sch, timing);

sys/dev/sdmmc/sdmmc_mem.c

862

int timing = SDMMC_TIMING_LEGACY;

sys/dev/sdmmc/sdmmc_mem.c

865

error = sdmmc_chip_bus_clock(sc->sct, sc->sch, speed, timing);

sys/dev/sdmmc/sdmmc_mem.c

886

timing = SDMMC_TIMING_MMC_HS200;

sys/dev/sdmmc/sdmmc_mem.c

890

timing = SDMMC_TIMING_MMC_DDR52;

sys/dev/sdmmc/sdmmc_mem.c

894

timing = SDMMC_TIMING_HIGHSPEED;

sys/dev/sdmmc/sdmmc_mem.c

929

if (timing != SDMMC_TIMING_LEGACY) {

sys/dev/sdmmc/sdmmc_mem.c

930

switch (timing) {

sys/dev/sdmmc/sdmmc_mem.c

952

KASSERT(timing < nitems(sdmmc_mmc_timings));

sys/dev/sdmmc/sdmmc_mem.c

953

sf->csd.tran_speed = sdmmc_mmc_timings[timing];

sys/dev/sdmmc/sdmmc_mem.c

955

if (timing != SDMMC_TIMING_LEGACY) {

sys/dev/sdmmc/sdmmc_mem.c

975

if (timing == SDMMC_TIMING_MMC_DDR52) {

sys/dev/sdmmc/sdmmcchip.h

68

#define sdmmc_chip_bus_clock(tag, handle, freq, timing) \

sys/dev/sdmmc/sdmmcchip.h

69

((tag)->bus_clock((handle), (freq), (timing)))

sys/dev/sdmmc/sdmmcchip.h

83

#define sdmmc_chip_execute_tuning(tag, handle, timing) \

sys/dev/sdmmc/sdmmcchip.h

84

((tag)->execute_tuning((handle), (timing)))