sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1129

case DC_SW_LINEAR:

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

636

GRPH_SW_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

641

GRPH_ARRAY_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

646

GRPH_ARRAY_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

165

case DC_SW_LINEAR:

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

258

case DC_SW_LINEAR:

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1257

case DC_SW_LINEAR:

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

319

case DC_SW_LINEAR:

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

526

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

414

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

342

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

565

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1216

enum swizzle_mode_values swizzle = DC_SW_LINEAR;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

404

if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {