DC_STATE_EN
intel_de_rmw(display, DC_STATE_EN,
intel_de_rmw(display, DC_STATE_EN, 0,
(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9),
intel_de_read(display, DC_STATE_EN) &
intel_de_read(display, DC_STATE_EN) &
intel_de_write(display, DC_STATE_EN, state);
v = intel_de_read(display, DC_STATE_EN);
intel_de_write(display, DC_STATE_EN, state);
val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);
val = intel_de_read(display, DC_STATE_EN);
intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
(intel_de_read(display, DC_STATE_EN) &
(intel_de_read(display, DC_STATE_EN) &
return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
MMIO_D(DC_STATE_EN);