libexec/talkd/table.c

56

typedef struct table_entry TABLE_ENTRY;

libexec/talkd/table.c

61

TAILQ_ENTRY(table_entry) list;

libexec/talkd/table.c

63

TAILQ_HEAD(, table_entry) table;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2206

struct wm_range_table_entry *table_entry,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2220

dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2221

dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2222

dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2244

struct wm_range_table_entry *table_entry;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2294

table_entry = &bw_params->wm_table.entries[WM_D];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2295

if (table_entry->wm_type == WM_TYPE_RETRAINING)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2299

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2302

table_entry = &bw_params->wm_table.entries[WM_C];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2304

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2307

table_entry = &bw_params->wm_table.entries[WM_B];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2309

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2313

table_entry = &bw_params->wm_table.entries[WM_A];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2315

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

293

struct wm_range_table_entry *table_entry,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

307

dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

308

dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

309

dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

434

struct wm_range_table_entry *table_entry;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

443

table_entry = &bw_params->wm_table.entries[WM_D];

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

444

if (table_entry->wm_type == WM_TYPE_RETRAINING)

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

448

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

451

table_entry = &bw_params->wm_table.entries[WM_C];

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

453

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

456

table_entry = &bw_params->wm_table.entries[WM_B];

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

458

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

462

table_entry = &bw_params->wm_table.entries[WM_A];

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

464

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,