Symbol: DC_LOG_DSC
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
176
DC_LOG_DSC("%s FEC at link encoder inst %d",
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
504
DC_LOG_DSC("dsc encoder caps:");
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
505
DC_LOG_DSC("\tdsc_version 0x%x", dsc_enc_caps.dsc_version);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
506
DC_LOG_DSC("\tslice_caps 0x%x", dsc_enc_caps.slice_caps.raw);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
507
DC_LOG_DSC("\tlb_bit_depth %d", dsc_enc_caps.lb_bit_depth);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
508
DC_LOG_DSC("\tis_block_pred_supported %d", dsc_enc_caps.is_block_pred_supported);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
509
DC_LOG_DSC("\tcolor_formats 0x%x", dsc_enc_caps.color_formats.raw);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
510
DC_LOG_DSC("\tcolor_depth 0x%x", dsc_enc_caps.color_depth.raw);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
511
DC_LOG_DSC("\tmax_total_throughput_mps %d", dsc_enc_caps.max_total_throughput_mps);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
512
DC_LOG_DSC("\tmax_slice_width %d", dsc_enc_caps.max_slice_width);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
513
DC_LOG_DSC("\tbpp_increment_div %d", dsc_enc_caps.bpp_increment_div);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
519
DC_LOG_DSC("dsc decoder caps:");
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
520
DC_LOG_DSC("\tis_dsc_supported %d", dsc_sink_caps->is_dsc_supported);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
521
DC_LOG_DSC("\tdsc_version 0x%x", dsc_sink_caps->dsc_version);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
522
DC_LOG_DSC("\trc_buffer_size %d", dsc_sink_caps->rc_buffer_size);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
523
DC_LOG_DSC("\tslice_caps1 0x%x", dsc_sink_caps->slice_caps1.raw);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
524
DC_LOG_DSC("\tslice_caps2 0x%x", dsc_sink_caps->slice_caps2.raw);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
525
DC_LOG_DSC("\tlb_bit_depth %d", dsc_sink_caps->lb_bit_depth);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
526
DC_LOG_DSC("\tis_block_pred_supported %d", dsc_sink_caps->is_block_pred_supported);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
527
DC_LOG_DSC("\tedp_max_bits_per_pixel %d", dsc_sink_caps->edp_max_bits_per_pixel);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
528
DC_LOG_DSC("\tcolor_formats 0x%x", dsc_sink_caps->color_formats.raw);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
529
DC_LOG_DSC("\tthroughput_mode_0_mps %d", dsc_sink_caps->throughput_mode_0_mps);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
530
DC_LOG_DSC("\tthroughput_mode_1_mps %d", dsc_sink_caps->throughput_mode_1_mps);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
531
DC_LOG_DSC("\tmax_slice_width %d", dsc_sink_caps->max_slice_width);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
532
DC_LOG_DSC("\tbpp_increment_div %d", dsc_sink_caps->bpp_increment_div);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
533
DC_LOG_DSC("\tbranch_overall_throughput_0_mps %d", dsc_sink_caps->branch_overall_throughput_0_mps);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
534
DC_LOG_DSC("\tbranch_overall_throughput_1_mps %d", dsc_sink_caps->branch_overall_throughput_1_mps);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
535
DC_LOG_DSC("\tbranch_max_line_width %d", dsc_sink_caps->branch_max_line_width);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
536
DC_LOG_DSC("\tis_dp %d", dsc_sink_caps->is_dp);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
173
DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
174
DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
175
DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
179
DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
188
DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
192
DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
207
DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
209
DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
226
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
231
DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
249
DC_LOG_DSC("disable DSC %d", dsc->inst);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
253
DC_LOG_DSC("DSC %d already disabled!", dsc->inst);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
274
DC_LOG_DSC("disconnect DSC %d", dsc->inst);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
286
DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
287
DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
288
DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
289
DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
290
DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
291
DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
292
DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
293
DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
294
DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
295
DC_LOG_DSC("\tpic_height %d", pps->pic_height);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
296
DC_LOG_DSC("\tpic_width %d", pps->pic_width);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
297
DC_LOG_DSC("\tslice_height %d", pps->slice_height);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
298
DC_LOG_DSC("\tslice_width %d", pps->slice_width);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
299
DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
300
DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
301
DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
302
DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
303
DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
304
DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
305
DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
306
DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
307
DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
308
DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
309
DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
310
DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
311
DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
313
DC_LOG_DSC("\tnative_420 %d", pps->native_420);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
314
DC_LOG_DSC("\tnative_422 %d", pps->native_422);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
315
DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
316
DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
317
DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
318
DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
319
DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
320
DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
321
DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
322
DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
323
DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
326
DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
329
DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
330
DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
331
DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
84
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
97
DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
129
DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
133
DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
145
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
150
DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
168
DC_LOG_DSC("disable DSC %d", dsc->inst);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
172
DC_LOG_DSC("DSC %d already disabled!", dsc->inst);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
193
DC_LOG_DSC("disconnect DSC %d", dsc->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
127
DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
90
DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
97
DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1044
DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1051
DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1084
DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
89
DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
347
DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
354
DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
383
DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
766
DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)",
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
768
DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
769
DC_LOG_DSC("\tslice_width %d", config->slice_width);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
864
DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
876
DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
977
DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1983
DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1984
DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1986
DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1988
DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2008
DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);