sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

139

DC_LOG_DEBUG("%s %x\n", __func__, smu_version);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

149

DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dispclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

164

DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

180

DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dcfclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

194

DC_LOG_DEBUG("%s(%d)\n", __func__, requested_min_ds_dcfclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

208

DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dpp_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

222

DC_LOG_DEBUG("%s(%x)\n", __func__, idle_info);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

239

DC_LOG_DEBUG("%s(%d)\n", __func__, enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

257

DC_LOG_DEBUG("%s(%x)\n", __func__, addr_high);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

265

DC_LOG_DEBUG("%s(%x)\n", __func__, addr_low);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

132

DC_LOG_DEBUG("Watermarks table not configured properly by SMU");

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

148

DC_LOG_DEBUG("Watermarks table not configured properly by SMU");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1786

DC_LOG_DEBUG("boot timing validation failed due to force_odm_combine\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1792

DC_LOG_DEBUG("boot timing validation failed due to disabled DIG\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1799

DC_LOG_DEBUG("boot timing validation failed due to unknown DIG engine ID\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1816

DC_LOG_DEBUG("boot timing validation failed due to timing generator instance not found\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1821

DC_LOG_DEBUG("boot timing validation failed due to invalid timing generator count\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1826

DC_LOG_DEBUG("boot timing validation failed due to non-preferred timing generator\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1833

DC_LOG_DEBUG("boot timing validation failed due to missing get_hw_timing callback\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1838

DC_LOG_DEBUG("boot timing validation failed due to failed get_hw_timing return\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1843

DC_LOG_DEBUG("boot timing validation failed due to h_total mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1848

DC_LOG_DEBUG("boot timing validation failed due to h_border_left mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1853

DC_LOG_DEBUG("boot timing validation failed due to h_addressable mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1858

DC_LOG_DEBUG("boot timing validation failed due to h_border_right mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1863

DC_LOG_DEBUG("boot timing validation failed due to h_front_porch mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1868

DC_LOG_DEBUG("boot timing validation failed due to h_sync_width mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1873

DC_LOG_DEBUG("boot timing validation failed due to v_total mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1878

DC_LOG_DEBUG("boot timing validation failed due to v_border_top mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1883

DC_LOG_DEBUG("boot timing validation failed due to v_addressable mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1888

DC_LOG_DEBUG("boot timing validation failed due to v_border_bottom mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1893

DC_LOG_DEBUG("boot timing validation failed due to v_front_porch mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1898

DC_LOG_DEBUG("boot timing validation failed due to v_sync_width mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1904

DC_LOG_DEBUG("boot timing validation failed due to DSC\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1929

DC_LOG_DEBUG("boot timing validation failed due to pixels_per_cycle\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1939

DC_LOG_DEBUG("boot timing validation failed due to pix_clk_100hz mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1944

DC_LOG_DEBUG("boot timing validation failed due to missing dp_get_pixel_format\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1952

DC_LOG_DEBUG("boot timing validation failed due to dp_get_pixel_format failure\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1957

DC_LOG_DEBUG("boot timing validation failed due to display_color_depth mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1962

DC_LOG_DEBUG("boot timing validation failed due to pixel_encoding mismatch\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1969

DC_LOG_DEBUG("boot timing validation failed due to VSC SDP colorimetry\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

1974

DC_LOG_DEBUG("boot timing validation failed due to DP 128b/132b\n");

sys/dev/pci/drm/amd/display/dc/core/dc.c

5590

DC_LOG_DEBUG("%s: disabled\n", __func__);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5611

DC_LOG_DEBUG("%s: %s\n", __func__, allow ? "enabled" : "disabled");

sys/dev/pci/drm/amd/display/dc/core/dc.c

6091

DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

410

DC_LOG_DEBUG("%s: CUR %s(%d) - enc_id(%d)\n",

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

423

DC_LOG_DEBUG("%s: NEW %s(%d) - enc_id(%d)\n",

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

743

DC_LOG_DEBUG("%s: current_state(%p) mode(%d)\n", __func__, current_state, LINK_ENC_CFG_TRANSIENT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1000

DC_LOG_DEBUG(" is_soft_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_soft_reset);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1001

DC_LOG_DEBUG(" is_secure_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_secure_reset);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1002

DC_LOG_DEBUG(" is_traceport_en : %d", dc_dmub_srv->dmub->debug.is_traceport_en);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1003

DC_LOG_DEBUG(" is_cw0_en : %d", dc_dmub_srv->dmub->debug.is_cw0_enabled);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1004

DC_LOG_DEBUG(" is_cw6_en : %d", dc_dmub_srv->dmub->debug.is_cw6_enabled);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1169

DC_LOG_DEBUG("Enabled DPIA trace\n");

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

278

DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

967

DC_LOG_DEBUG("DMCUB STATE:");

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

968

DC_LOG_DEBUG(" dmcub_version : %08x", dc_dmub_srv->dmub->debug.dmcub_version);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

969

DC_LOG_DEBUG(" scratch [0] : %08x", dc_dmub_srv->dmub->debug.scratch[0]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

970

DC_LOG_DEBUG(" scratch [1] : %08x", dc_dmub_srv->dmub->debug.scratch[1]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

971

DC_LOG_DEBUG(" scratch [2] : %08x", dc_dmub_srv->dmub->debug.scratch[2]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

972

DC_LOG_DEBUG(" scratch [3] : %08x", dc_dmub_srv->dmub->debug.scratch[3]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

973

DC_LOG_DEBUG(" scratch [4] : %08x", dc_dmub_srv->dmub->debug.scratch[4]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

974

DC_LOG_DEBUG(" scratch [5] : %08x", dc_dmub_srv->dmub->debug.scratch[5]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

975

DC_LOG_DEBUG(" scratch [6] : %08x", dc_dmub_srv->dmub->debug.scratch[6]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

976

DC_LOG_DEBUG(" scratch [7] : %08x", dc_dmub_srv->dmub->debug.scratch[7]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

977

DC_LOG_DEBUG(" scratch [8] : %08x", dc_dmub_srv->dmub->debug.scratch[8]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

978

DC_LOG_DEBUG(" scratch [9] : %08x", dc_dmub_srv->dmub->debug.scratch[9]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

979

DC_LOG_DEBUG(" scratch [10] : %08x", dc_dmub_srv->dmub->debug.scratch[10]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

980

DC_LOG_DEBUG(" scratch [11] : %08x", dc_dmub_srv->dmub->debug.scratch[11]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

981

DC_LOG_DEBUG(" scratch [12] : %08x", dc_dmub_srv->dmub->debug.scratch[12]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

982

DC_LOG_DEBUG(" scratch [13] : %08x", dc_dmub_srv->dmub->debug.scratch[13]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

983

DC_LOG_DEBUG(" scratch [14] : %08x", dc_dmub_srv->dmub->debug.scratch[14]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

984

DC_LOG_DEBUG(" scratch [15] : %08x", dc_dmub_srv->dmub->debug.scratch[15]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

986

DC_LOG_DEBUG(" pc[%d] : %08x", i, dc_dmub_srv->dmub->debug.pc[i]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

987

DC_LOG_DEBUG(" unk_fault_addr : %08x", dc_dmub_srv->dmub->debug.undefined_address_fault_addr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

988

DC_LOG_DEBUG(" inst_fault_addr : %08x", dc_dmub_srv->dmub->debug.inst_fetch_fault_addr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

989

DC_LOG_DEBUG(" data_fault_addr : %08x", dc_dmub_srv->dmub->debug.data_write_fault_addr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

990

DC_LOG_DEBUG(" inbox1_rptr : %08x", dc_dmub_srv->dmub->debug.inbox1_rptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

991

DC_LOG_DEBUG(" inbox1_wptr : %08x", dc_dmub_srv->dmub->debug.inbox1_wptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

992

DC_LOG_DEBUG(" inbox1_size : %08x", dc_dmub_srv->dmub->debug.inbox1_size);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

993

DC_LOG_DEBUG(" inbox0_rptr : %08x", dc_dmub_srv->dmub->debug.inbox0_rptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

994

DC_LOG_DEBUG(" inbox0_wptr : %08x", dc_dmub_srv->dmub->debug.inbox0_wptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

995

DC_LOG_DEBUG(" inbox0_size : %08x", dc_dmub_srv->dmub->debug.inbox0_size);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

996

DC_LOG_DEBUG(" outbox1_rptr : %08x", dc_dmub_srv->dmub->debug.outbox1_rptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

997

DC_LOG_DEBUG(" outbox1_wptr : %08x", dc_dmub_srv->dmub->debug.outbox1_wptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

998

DC_LOG_DEBUG(" outbox1_size : %08x", dc_dmub_srv->dmub->debug.outbox1_size);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

999

DC_LOG_DEBUG(" is_enabled : %d", dc_dmub_srv->dmub->debug.is_dmcub_enabled);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1140

DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1410

DC_LOG_DEBUG("%s: OTG%d DTBCLK DTO enabled: pixclk_khz=%d, ref_dtbclk_khz=%d, req_dtbclk_khz=%d, phase=%d, modulo=%d\n",

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1440

DC_LOG_DEBUG("%s: OTG%d DTBCLK DTO disabled\n", __func__, params->otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1485

DC_LOG_DEBUG("%s: dp_hpo_inst(%d) DPSTREAMCLK_EN = %d, DPSTREAMCLK_SRC_SEL = %d\n",

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1526

DC_LOG_DEBUG("%s: dp_hpo_inst(%d) DPSTREAMCLK_ROOT_GATE_DISABLE = %d\n",

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1567

DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE: %d\n", __func__, phy_inst, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1640

DC_LOG_DEBUG("%s: phy_inst(%d) PHYxSYMCLK_EN = %d, PHYxSYMCLK_SRC_SEL = %d\n",

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1689

DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1770

DC_LOG_DEBUG("%s: OTG%d SYMCLK32_LE disabled and root clock gating disabled\n",

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1784

DC_LOG_DEBUG("%s: OTG%d DPSTREAMCLK disabled and root clock gating disabled\n",

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

515

DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n");

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

522

DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

528

DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

537

DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

543

DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

551

DC_LOG_DEBUG("HDMI source deep color depth enabled in" \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

460

DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

492

DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

507

DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

539

DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

553

DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

585

DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

310

DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

325

DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

339

DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

367

DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

387

DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

106

DC_LOG_DEBUG("Set DET%d to %d segments\n", hubp_inst, det_size_segments);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1370

DC_LOG_DEBUG("DML Validation | Running Validation");

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1400

DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1403

DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1406

DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1409

DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1412

DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1416

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1419

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1422

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1425

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1428

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1431

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1434

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1437

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1441

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1444

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1447

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1450

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1453

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1456

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1459

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1462

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1480

DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1483

DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1486

DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1489

DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1492

DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1495

DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1498

DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1538

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1541

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1544

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1547

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1550

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1553

DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1556

DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1559

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1562

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1565

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1568

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1571

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1574

DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1577

DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1580

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1583

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1592

DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1595

DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1624

DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1627

DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1630

DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1633

DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1636

DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1639

DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1642

DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1645

DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1648

DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1651

DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1654

DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1657

DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1660

DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1663

DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

264

DC_LOG_DEBUG("DML Validation | Running Validation");

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

293

DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

296

DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

299

DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

302

DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

305

DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

309

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

312

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

315

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

318

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

321

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

324

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

327

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

330

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

334

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

337

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

340

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

343

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

346

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

349

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

352

DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

371

DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

374

DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

377

DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

380

DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

383

DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

386

DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

389

DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

429

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

432

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

435

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

438

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

441

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

444

DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

447

DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

450

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

453

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

456

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

459

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

462

DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

465

DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

468

DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

471

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

474

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

483

DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

486

DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

515

DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

518

DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

521

DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

524

DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

527

DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

530

DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

533

DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

536

DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

539

DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

542

DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

545

DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

548

DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

551

DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

554

DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

574

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

577

DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

580

DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

583

DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

586

DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

589

DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

592

DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n",

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1028

DC_LOG_DEBUG(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1345

DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1509

DC_LOG_DEBUG(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1307

DC_LOG_DEBUG(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2897

DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

609

DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1895

DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2678

DC_LOG_DEBUG(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1407

DC_LOG_DEBUG("Unknown encoding format\n");

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2316

DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2566

DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

507

DC_LOG_DEBUG("Set retimer failed");

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

630

DC_LOG_DEBUG("Set default retimer failed");

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

659

DC_LOG_DEBUG("Set redriver failed");

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

129

DC_LOG_DEBUG("%s: for link(%d) dpia(%d) success, current_hpd_status(%d) new_hpd_status(%d)\n",

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

89

DC_LOG_DEBUG("%s: Link[%d] DP tunneling support (RouterId=%d AdapterId=%d) "

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

156

DC_LOG_DEBUG("%s: bw_granularity(%d), estimated_bw(%d)\n",

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

159

DC_LOG_DEBUG("%s: nrd_max_link_rate(%d), nrd_max_lane_count(%d)\n",

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

175

DC_LOG_DEBUG("%s: resetting BW alloc config for link(%d)\n",

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

229

DC_LOG_DEBUG("%s: link[%d] DPTX BW allocation mode disabled", __func__, link->link_index);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

236

DC_LOG_DEBUG("%s: link[%d] DPTX BW allocation mode enabled", __func__, link->link_index);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

261

DC_LOG_DEBUG("%s: link[%d] failed to enable DPTX BW allocation mode", __func__, link->link_index);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

279

DC_LOG_DEBUG("%s: BW Allocation request succeeded on link(%d)",

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

282

DC_LOG_DEBUG("%s: BW Allocation request failed on link(%d) allocated/estimated BW=%d",

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

287

DC_LOG_DEBUG("%s: Estimated BW changed on link(%d) new estimated BW=%d",

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

318

DC_LOG_DEBUG("%s: ENTER: link[%d] hpd(%d) Allocated_BW: %d Estimated_BW: %d Req_BW: %d",

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

327

DC_LOG_DEBUG("%s: BW Allocation mode not available", __func__);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

69

DC_LOG_DEBUG("reset usb4 bw alloc of link(%d)\n", link->link_index);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

229

DC_LOG_DEBUG("HUBP DPP instance %d, power %s", hubp_dpp_inst,

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

500

DC_LOG_DEBUG("%s: %s", debug_func, debug_log);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

502

DC_LOG_DEBUG("PG_CNTL status:\n");

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

505

DC_LOG_DEBUG("ONO0=%d (DCCG, DIO, DCIO)\n", block_enabled ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

508

DC_LOG_DEBUG("ONO1=%d (DCHUBBUB, DCHVM, DCHUBBUBMEM)\n", block_enabled ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

511

DC_LOG_DEBUG("ONO2=%d (MPC, OPP, OPTC, DWB)\n", block_enabled ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

514

DC_LOG_DEBUG("ONO3=%d (HPO)\n", block_enabled ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

518

DC_LOG_DEBUG("ONO%d=%d (DCHUBP%d, DPP%d)\n", 4 + i * 2, block_enabled ? 1 : 0, i, i);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

521

DC_LOG_DEBUG("ONO%d=%d (DSC%d)\n", 5 + i * 2, block_enabled ? 1 : 0, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1593

DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);