sys/arch/amd64/amd64/vmm_machdep.c

145

void svm_setmsrbrw(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

1614

svm_setmsrbrw(vcpu, MSR_IA32_FEATURE_CONTROL);

sys/arch/amd64/amd64/vmm_machdep.c

1615

svm_setmsrbrw(vcpu, MSR_SYSENTER_CS);

sys/arch/amd64/amd64/vmm_machdep.c

1616

svm_setmsrbrw(vcpu, MSR_SYSENTER_ESP);

sys/arch/amd64/amd64/vmm_machdep.c

1617

svm_setmsrbrw(vcpu, MSR_SYSENTER_EIP);

sys/arch/amd64/amd64/vmm_machdep.c

1618

svm_setmsrbrw(vcpu, MSR_STAR);

sys/arch/amd64/amd64/vmm_machdep.c

1619

svm_setmsrbrw(vcpu, MSR_LSTAR);

sys/arch/amd64/amd64/vmm_machdep.c

1620

svm_setmsrbrw(vcpu, MSR_CSTAR);

sys/arch/amd64/amd64/vmm_machdep.c

1621

svm_setmsrbrw(vcpu, MSR_SFMASK);

sys/arch/amd64/amd64/vmm_machdep.c

1622

svm_setmsrbrw(vcpu, MSR_FSBASE);

sys/arch/amd64/amd64/vmm_machdep.c

1623

svm_setmsrbrw(vcpu, MSR_GSBASE);

sys/arch/amd64/amd64/vmm_machdep.c

1624

svm_setmsrbrw(vcpu, MSR_KERNELGSBASE);

sys/arch/amd64/amd64/vmm_machdep.c

1627

svm_setmsrbrw(vcpu, MSR_SEV_STATUS);

sys/arch/amd64/amd64/vmm_machdep.c

1631

svm_setmsrbrw(vcpu, MSR_SEV_GHCB);

sys/arch/amd64/amd64/vmm_machdep.c

1641

svm_setmsrbrw(vcpu, MSR_EFER);