regress/lib/libc/sys/t_mkfifo.c

126

support();

regress/lib/libc/sys/t_mkfifo.c

165

support();

regress/lib/libc/sys/t_mkfifo.c

218

support();

regress/lib/libc/sys/t_mkfifo.c

249

support();

regress/lib/libc/sys/t_mkfifo.c

277

support();

regress/lib/libc/sys/t_mkfifo.c

48

static void support(void);

regress/lib/libc/sys/t_mkfifo.c

79

support();

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

320

void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

328

(support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

329

support = DCN_ZSTATE_SUPPORT_DISALLOW;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

331

if (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY ||

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

332

support == DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

337

if (support == DCN_ZSTATE_SUPPORT_DISALLOW)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

268

void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

339

void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

346

switch (support) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

107

void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

361

void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

368

switch (support) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

210

void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1020

block_sequence[num_steps].params.update_pstate_support_params.support = false;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

711

params->update_pstate_support_params.support);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

716

params->update_pstate_support_params.support);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

909

block_sequence[num_steps].params.update_pstate_support_params.support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

40

bool support;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

199

void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

201

smu_print("FCLK P-state support value is : %d\n", support);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

204

DALSMC_MSG_SetFclkSwitchAllow, support, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

207

void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

209

smu_print("UCLK P-state support value is : %d\n", support);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

212

DALSMC_MSG_SetUclkPstateAllow, support, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

16

void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

17

void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

580

enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

592

support = DCN_ZSTATE_SUPPORT_ALLOW;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

608

support = DCN_ZSTATE_SUPPORT_ALLOW;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

610

support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

612

support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

616

DC_LOG_SMU("zstate_support: %d, StutterPeriod: %d\n", support,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

619

context->bw_ctx.bw.dcn.clk.zstate_support = support;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

613

enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

623

support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

636

support = allow_z8 ? allow_z8 : DCN_ZSTATE_SUPPORT_DISALLOW;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

638

context->bw_ctx.bw.dcn.clk.zstate_support = support;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10145

mode_lib->ms.support.ImmediateFlipSupport = 1; // assume mode support say immediate flip ok at max state/combine

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10196

*in_out_params->out_evaluation_info = in_out_params->mode_lib->ms.support;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6266

CalculatePrefetchSchedule_params->NotEnoughTimeForDynamicMetadata = &mode_lib->ms.support.NoTimeForDynamicMetadata[j][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6296

mode_lib->ms.support.VActiveBandwithSupport[j] = CalculateVActiveBandwithSupport(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6413

mode_lib->ms.support.NoTimeForPrefetch[j][k] =

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6474

&mode_lib->ms.support.PrefetchSupported[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6481

|| mode_lib->ms.support.NoTimeForPrefetch[j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6482

mode_lib->ms.support.PrefetchSupported[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6486

mode_lib->ms.support.DynamicMetadataSupported[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6488

if (mode_lib->ms.support.NoTimeForDynamicMetadata[j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6489

mode_lib->ms.support.DynamicMetadataSupported[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6493

mode_lib->ms.support.VRatioInPrefetchSupported[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6495

if (mode_lib->ms.support.NoTimeForPrefetch[j][k] == true ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6500

mode_lib->ms.support.VRatioInPrefetchSupported[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6511

if (mode_lib->ms.support.PrefetchSupported[j] == true && mode_lib->ms.support.VRatioInPrefetchSupported[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6602

&mode_lib->ms.support.ImmediateFlipSupportedForState[j]); // dml_bool_t *ImmediateFlipBandwidthSupport

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6607

mode_lib->ms.support.ImmediateFlipSupportedForState[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6611

mode_lib->ms.support.ImmediateFlipSupportedForState[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6625

} while (!((mode_lib->ms.support.PrefetchSupported[j] == true && mode_lib->ms.support.DynamicMetadataSupported[j] == true &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6626

mode_lib->ms.support.VRatioInPrefetchSupported[j] == true &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6629

((s->ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j] == true)) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6700

CalculateWatermarks_params->DRAMClockChangeSupport = &mode_lib->ms.support.DRAMClockChangeSupport[j];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6703

CalculateWatermarks_params->FCLKChangeSupport = &mode_lib->ms.support.FCLKChangeSupport[j];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6705

CalculateWatermarks_params->USRRetrainingSupport = &mode_lib->ms.support.USRRetrainingSupport[j];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6706

CalculateWatermarks_params->ActiveDRAMClockChangeLatencyMargin = mode_lib->ms.support.ActiveDRAMClockChangeLatencyMargin;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6746

mode_lib->ms.support.ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6760

mode_lib->ms.support.ScaleRatioAndTapsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6780

mode_lib->ms.support.ScaleRatioAndTapsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6785

mode_lib->ms.support.SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6788

mode_lib->ms.support.SourceFormatPixelAndScanSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6846

mode_lib->ms.support.WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6850

mode_lib->ms.support.WritebackLatencySupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6862

mode_lib->ms.support.EnoughWritebackUnits = 1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6864

mode_lib->ms.support.EnoughWritebackUnits = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6868

mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6880

mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6883

mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6948

mode_lib->ms.support.NumberOfDSCSlices[k] = mode_lib->ms.cache_display_cfg.output.DSCSlices[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6950

if (mode_lib->ms.support.NumberOfDSCSlices[k] == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6952

mode_lib->ms.support.NumberOfDSCSlices[k] = (dml_uint_t)(dml_ceil(mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 600, 4));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6954

mode_lib->ms.support.NumberOfDSCSlices[k] = 8;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6956

mode_lib->ms.support.NumberOfDSCSlices[k] = 4;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6958

mode_lib->ms.support.NumberOfDSCSlices[k] = 2;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6960

mode_lib->ms.support.NumberOfDSCSlices[k] = 1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6964

mode_lib->ms.support.NumberOfDSCSlices[k] = 1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7041

mode_lib->ms.support.MPCCombineMethodIncompatible = s->MPCCombineMethodAsNeededForPStateChangeAndVoltage && s->MPCCombineMethodAsPossible;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7045

mode_lib->ms.support.TotalAvailablePipesSupport[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7063

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7086

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7107

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7128

mode_lib->ms.support.TotalAvailablePipesSupport[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7134

mode_lib->ms.support.TotalAvailablePipesSupport[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7161

mode_lib->ms.support.TotalAvailablePipesSupport[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7242

mode_lib->ms.support.DISPCLK_DPPCLK_Support[j] = !((mode_lib->ms.RequiredDISPCLK[j] > mode_lib->ms.state.dispclk_mhz) || (mode_lib->ms.GlobalDPPCLK > mode_lib->ms.state.dppclk_mhz));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7245

mode_lib->ms.support.TotalAvailablePipesSupport[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7269

mode_lib->ms.support.NumberOfOTGSupport = (s->TotalNumberOfActiveOTG <= (dml_uint_t) mode_lib->ms.ip.max_num_otg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7270

mode_lib->ms.support.NumberOfHDMIFRLSupport = (s->TotalNumberOfActiveHDMIFRL <= (dml_uint_t) mode_lib->ms.ip.max_num_hdmi_frl_outputs);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7271

mode_lib->ms.support.NumberOfDP2p0Support = (s->TotalNumberOfActiveDP2p0 <= (dml_uint_t) mode_lib->ms.ip.max_num_dp2p0_streams && s->TotalNumberOfActiveDP2p0Outputs <= (dml_uint_t) mode_lib->ms.ip.max_num_dp2p0_outputs);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7274

mode_lib->ms.support.NonsupportedDSCInputBPC = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7282

mode_lib->ms.support.NonsupportedDSCInputBPC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7286

mode_lib->ms.support.ExceededMultistreamSlots = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7295

mode_lib->ms.support.ExceededMultistreamSlots = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7297

mode_lib->ms.support.ExceededMultistreamSlots = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7300

mode_lib->ms.support.LinkCapacitySupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7305

mode_lib->ms.support.LinkCapacitySupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7309

mode_lib->ms.support.P2IWith420 = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7310

mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7311

mode_lib->ms.support.DSC422NativeNotSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7312

mode_lib->ms.support.LinkRateDoesNotMatchDPVersion = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7313

mode_lib->ms.support.LinkRateForMultistreamNotIndicated = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7314

mode_lib->ms.support.BPPForMultistreamNotIndicated = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7315

mode_lib->ms.support.MultistreamWithHDMIOreDP = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7316

mode_lib->ms.support.MSOOrODMSplitWithNonDPLink = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7317

mode_lib->ms.support.NotEnoughLanesForMSO = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7323

mode_lib->ms.support.P2IWith420 = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7326

mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7328

mode_lib->ms.support.DSC422NativeNotSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7334

mode_lib->ms.support.LinkRateDoesNotMatchDPVersion = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7338

mode_lib->ms.support.LinkRateForMultistreamNotIndicated = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7340

mode_lib->ms.support.BPPForMultistreamNotIndicated = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7343

mode_lib->ms.support.BPPForMultistreamNotIndicated = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7349

mode_lib->ms.support.MultistreamWithHDMIOreDP = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7352

mode_lib->ms.support.MultistreamWithHDMIOreDP = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7357

mode_lib->ms.support.MSOOrODMSplitWithNonDPLink = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7361

mode_lib->ms.support.NotEnoughLanesForMSO = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7365

mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7374

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7379

mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7383

mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7384

mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7387

mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7391

mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7395

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7422

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7426

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7430

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7438

dml_print("DML::%s: DSCCLKRequiredMoreThanSupported = %u\n", __func__, mode_lib->ms.support.DSCCLKRequiredMoreThanSupported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7442

mode_lib->ms.support.NotEnoughDSCUnits = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7443

mode_lib->ms.support.NotEnoughDSCSlices = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7445

mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7450

mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7452

if (mode_lib->ms.support.NumberOfDSCSlices[k] > 16)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7453

mode_lib->ms.support.NotEnoughDSCSlices = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7456

mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7458

if (mode_lib->ms.support.NumberOfDSCSlices[k] > 8)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7459

mode_lib->ms.support.NotEnoughDSCSlices = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7462

mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7464

if (mode_lib->ms.support.NumberOfDSCSlices[k] > 4)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7465

mode_lib->ms.support.NotEnoughDSCSlices = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7470

mode_lib->ms.support.NotEnoughDSCUnits = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7481

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7567

CalculateSwathAndDETConfiguration_params->ViewportSizeSupport = &mode_lib->ms.support.ViewportSizeSupport[j];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7622

&mode_lib->ms.support.ExceededMALLSize);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7765

mode_lib->ms.support.PTEBufferSizeNotExceeded[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7769

mode_lib->ms.support.PTEBufferSizeNotExceeded[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7775

dml_print("DML::%s: PTEBufferSizeNotExceeded[%u] = %u\n", __func__, j, mode_lib->ms.support.PTEBufferSizeNotExceeded[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7778

mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7781

mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7914

mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7916

mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7920

mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified && s->ImmediateFlipRequiredFinal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7922

mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7924

mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe =

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7925

mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe || ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == true || mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7929

mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7931

mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen = mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7951

mode_lib->ms.support.InvalidCombinationOfMALLUseForPState = (s->SubViewportMALLPStateMethod != s->PhantomPipeMALLPStateMethod)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8028

mode_lib->ms.support.ROBSupport[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8030

mode_lib->ms.support.ROBSupport[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8032

dml_print("DML::%s: DEBUG ROBSupport[%u] = %u (%u)\n", __func__, j, mode_lib->ms.support.ROBSupport[j], __LINE__);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8042

mode_lib->ms.support.MaxTotalVerticalActiveAvailableBandwidth[j] = dml_min3(mode_lib->ms.soc.return_bus_width_bytes * mode_lib->ms.DCFCLKState[j] * mode_lib->ms.soc.max_avg_sdp_bw_use_normal_percent / 100.0,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8048

if (s->MaxTotalVActiveRDBandwidth <= mode_lib->ms.support.MaxTotalVerticalActiveAvailableBandwidth[j]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8049

mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8051

mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8062

mode_lib->ms.support.CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8066

mode_lib->ms.support.CursorSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8072

mode_lib->ms.support.PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8074

mode_lib->ms.support.AlignedYPitch[k] = dml_ceil(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8078

mode_lib->ms.support.AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k]), 64.0 * mode_lib->ms.Read256BlockWidthY[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8080

mode_lib->ms.support.AlignedDCCMetaPitchY[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8088

mode_lib->ms.support.AlignedCPitch[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.PitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), mode_lib->ms.MacroTileWidthC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8090

mode_lib->ms.support.AlignedDCCMetaPitchC[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), 64.0 * mode_lib->ms.Read256BlockWidthC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8092

mode_lib->ms.support.AlignedDCCMetaPitchC[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8095

mode_lib->ms.support.AlignedCPitch[k] = mode_lib->ms.cache_display_cfg.surface.PitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8096

mode_lib->ms.support.AlignedDCCMetaPitchC[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8098

if (mode_lib->ms.support.AlignedYPitch[k] > mode_lib->ms.cache_display_cfg.surface.PitchY[k] || mode_lib->ms.support.AlignedCPitch[k] > mode_lib->ms.cache_display_cfg.surface.PitchC[k] ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8099

mode_lib->ms.support.AlignedDCCMetaPitchY[k] > mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k] || mode_lib->ms.support.AlignedDCCMetaPitchC[k] > mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8100

mode_lib->ms.support.PitchSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8104

mode_lib->ms.support.ViewportExceedsSurface = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8107

mode_lib->ms.support.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8111

mode_lib->ms.support.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8127

mode_lib->ms.support.DRAMClockChangeSupport[j] != dml_dram_clock_change_unsupported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8130

mode_lib->ms.support.FCLKChangeSupport[j] != dml_fclock_change_unsupported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8132

if (mode_lib->ms.support.ScaleRatioAndTapsSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8133

&& mode_lib->ms.support.SourceFormatPixelAndScanSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8134

&& mode_lib->ms.support.ViewportSizeSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8135

&& !mode_lib->ms.support.LinkRateDoesNotMatchDPVersion

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8136

&& !mode_lib->ms.support.LinkRateForMultistreamNotIndicated

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8137

&& !mode_lib->ms.support.BPPForMultistreamNotIndicated

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8138

&& !mode_lib->ms.support.MultistreamWithHDMIOreDP

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8139

&& !mode_lib->ms.support.ExceededMultistreamSlots

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8140

&& !mode_lib->ms.support.MSOOrODMSplitWithNonDPLink

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8141

&& !mode_lib->ms.support.NotEnoughLanesForMSO

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8142

&& mode_lib->ms.support.LinkCapacitySupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8143

&& !mode_lib->ms.support.P2IWith420

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8144

&& !mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8145

&& !mode_lib->ms.support.DSC422NativeNotSupported

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8146

&& !mode_lib->ms.support.MPCCombineMethodIncompatible

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8147

&& mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8148

&& mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8149

&& mode_lib->ms.support.NotEnoughDSCUnits == false

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8150

&& !mode_lib->ms.support.NotEnoughDSCSlices

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8151

&& !mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8152

&& !mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8153

&& mode_lib->ms.support.DSCCLKRequiredMoreThanSupported == false

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8154

&& mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8155

&& mode_lib->ms.support.DTBCLKRequiredMoreThanSupported == false

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8156

&& !mode_lib->ms.support.InvalidCombinationOfMALLUseForPState

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8157

&& !mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8158

&& mode_lib->ms.support.ROBSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8159

&& mode_lib->ms.support.DISPCLK_DPPCLK_Support[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8160

&& mode_lib->ms.support.TotalAvailablePipesSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8161

&& mode_lib->ms.support.NumberOfOTGSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8162

&& mode_lib->ms.support.NumberOfHDMIFRLSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8163

&& mode_lib->ms.support.NumberOfDP2p0Support == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8164

&& mode_lib->ms.support.EnoughWritebackUnits == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8165

&& mode_lib->ms.support.WritebackLatencySupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8166

&& mode_lib->ms.support.WritebackScaleRatioAndTapsSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8167

&& mode_lib->ms.support.CursorSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8168

&& mode_lib->ms.support.PitchSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8169

&& mode_lib->ms.support.ViewportExceedsSurface == false

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8170

&& mode_lib->ms.support.PrefetchSupported[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8171

&& mode_lib->ms.support.VActiveBandwithSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8172

&& mode_lib->ms.support.DynamicMetadataSupported[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8173

&& mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8174

&& mode_lib->ms.support.VRatioInPrefetchSupported[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8175

&& mode_lib->ms.support.PTEBufferSizeNotExceeded[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8176

&& mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8177

&& mode_lib->ms.support.NonsupportedDSCInputBPC == false

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8178

&& !mode_lib->ms.support.ExceededMALLSize

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8179

&& ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !s->ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8182

&& (!mode_lib->ms.policy.USRRetrainingRequiredFinal || mode_lib->ms.support.USRRetrainingSupport[j])) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8184

mode_lib->ms.support.ModeSupport[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8187

mode_lib->ms.support.ModeSupport[j] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8192

mode_lib->ms.support.MaximumMPCCombine = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8193

mode_lib->ms.support.ModeIsSupported = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8194

if (mode_lib->ms.support.ModeSupport[0] == true || mode_lib->ms.support.ModeSupport[1] == true) { // if the mode is supported by either no combine or mpccombine

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8195

mode_lib->ms.support.ModeIsSupported = mode_lib->ms.support.ModeSupport[0] == true || mode_lib->ms.support.ModeSupport[1] == true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8198

if ((mode_lib->ms.support.ModeSupport[0] == false && mode_lib->ms.support.ModeSupport[1] == true) || s->MPCCombineMethodAsPossible ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8200

(((mode_lib->ms.support.DRAMClockChangeSupport[1] == dml_dram_clock_change_vactive || mode_lib->ms.support.DRAMClockChangeSupport[1] == dml_dram_clock_change_vactive_w_mall_full_frame || mode_lib->ms.support.DRAMClockChangeSupport[1] == dml_dram_clock_change_vactive_w_mall_sub_vp) &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8201

!(mode_lib->ms.support.DRAMClockChangeSupport[0] == dml_dram_clock_change_vactive || mode_lib->ms.support.DRAMClockChangeSupport[0] == dml_dram_clock_change_vactive_w_mall_full_frame || mode_lib->ms.support.DRAMClockChangeSupport[0] == dml_dram_clock_change_vactive_w_mall_sub_vp)) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8202

((mode_lib->ms.support.DRAMClockChangeSupport[1] == dml_dram_clock_change_vblank || mode_lib->ms.support.DRAMClockChangeSupport[1] == dml_dram_clock_change_vblank_drr

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8203

|| mode_lib->ms.support.DRAMClockChangeSupport[1] == dml_dram_clock_change_vblank_w_mall_full_frame || mode_lib->ms.support.DRAMClockChangeSupport[1] == dml_dram_clock_change_vblank_drr_w_mall_full_frame

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8204

|| mode_lib->ms.support.DRAMClockChangeSupport[1] == dml_dram_clock_change_vblank_w_mall_sub_vp || mode_lib->ms.support.DRAMClockChangeSupport[1] == dml_dram_clock_change_vblank_drr_w_mall_sub_vp

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8206

mode_lib->ms.support.DRAMClockChangeSupport[0] == dml_dram_clock_change_unsupported)))

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8208

((mode_lib->ms.support.FCLKChangeSupport[1] == dml_fclock_change_vactive && mode_lib->ms.support.FCLKChangeSupport[0] != dml_fclock_change_vactive) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8209

(mode_lib->ms.support.FCLKChangeSupport[1] == dml_fclock_change_vblank && mode_lib->ms.support.FCLKChangeSupport[0] == dml_fclock_change_unsupported)))) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8210

mode_lib->ms.support.MaximumMPCCombine = 1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8212

mode_lib->ms.support.MaximumMPCCombine = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8217

mode_lib->ms.support.ImmediateFlipSupport = mode_lib->ms.support.ImmediateFlipSupportedForState[mode_lib->ms.support.MaximumMPCCombine]; // Consider flip support if max combine support imm flip

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8218

mode_lib->ms.support.UnboundedRequestEnabled = mode_lib->ms.UnboundedRequestEnabledAllStates[mode_lib->ms.support.MaximumMPCCombine]; // Not used, informational

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8219

mode_lib->ms.support.CompressedBufferSizeInkByte = mode_lib->ms.CompressedBufferSizeInkByteAllStates[mode_lib->ms.support.MaximumMPCCombine]; // Not used, informational

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8221

dml_print("DML::%s: ModeIsSupported = %u\n", __func__, mode_lib->ms.support.ModeIsSupported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8222

dml_print("DML::%s: MaximumMPCCombine = %u\n", __func__, mode_lib->ms.support.MaximumMPCCombine);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8223

dml_print("DML::%s: ImmediateFlipSupport = %u\n", __func__, mode_lib->ms.support.ImmediateFlipSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8224

dml_print("DML::%s: UnboundedRequestEnabled = %u\n", __func__, mode_lib->ms.support.UnboundedRequestEnabled);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8225

dml_print("DML::%s: CompressedBufferSizeInkByte = %u\n", __func__, mode_lib->ms.support.CompressedBufferSizeInkByte);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8228

mode_lib->ms.support.MPCCombineEnable[k] = mode_lib->ms.MPCCombine[mode_lib->ms.support.MaximumMPCCombine][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8229

mode_lib->ms.support.DPPPerSurface[k] = mode_lib->ms.NoOfDPP[mode_lib->ms.support.MaximumMPCCombine][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8230

mode_lib->ms.SwathHeightY[k] = mode_lib->ms.SwathHeightYAllStates[mode_lib->ms.support.MaximumMPCCombine][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8231

mode_lib->ms.SwathHeightC[k] = mode_lib->ms.SwathHeightCAllStates[mode_lib->ms.support.MaximumMPCCombine][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8232

mode_lib->ms.DETBufferSizeInKByte[k] = mode_lib->ms.DETBufferSizeInKByteAllStates[mode_lib->ms.support.MaximumMPCCombine][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8233

mode_lib->ms.DETBufferSizeY[k] = mode_lib->ms.DETBufferSizeYAllStates[mode_lib->ms.support.MaximumMPCCombine][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8234

mode_lib->ms.DETBufferSizeC[k] = mode_lib->ms.DETBufferSizeCAllStates[mode_lib->ms.support.MaximumMPCCombine][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8240

mode_lib->ms.DCFCLK = mode_lib->ms.DCFCLKState[mode_lib->ms.support.MaximumMPCCombine];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8241

mode_lib->ms.ReturnBW = mode_lib->ms.ReturnBWPerState[mode_lib->ms.support.MaximumMPCCombine];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8242

mode_lib->ms.ReturnDRAMBW = mode_lib->ms.ReturnDRAMBWPerState[mode_lib->ms.support.MaximumMPCCombine];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8246

mode_lib->ms.support.ODMMode[k] = mode_lib->ms.ODMModePerState[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8248

mode_lib->ms.support.ODMMode[k] = dml_odm_mode_bypass;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8251

mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8252

mode_lib->ms.support.FECEnabled[k] = mode_lib->ms.RequiresFEC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8253

mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBppPerState[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8254

mode_lib->ms.support.OutputType[k] = mode_lib->ms.OutputTypePerState[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8255

mode_lib->ms.support.OutputRate[k] = mode_lib->ms.OutputRatePerState[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8256

mode_lib->ms.support.SubViewportLinesNeededInMALL[k] = mode_lib->ms.SubViewportLinesNeededInMALL[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8259

return mode_lib->ms.support.ModeIsSupported;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8331

dml_print("DML::%s: ImmediateFlipSupport = %u\n", __func__, mode_lib->ms.support.ImmediateFlipSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9212

if (locals->PrefetchModeSupported == true && mode_lib->ms.support.ImmediateFlipSupport == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9357

((!mode_lib->ms.support.ImmediateFlipSupport && !mode_lib->ms.cache_display_cfg.plane.HostVMEnable && !s->ImmediateFlipRequirementFinal) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9365

dml_print("DML::%s: ImmediateFlipSupport = %u (from mode_support)\n", __func__, mode_lib->ms.support.ImmediateFlipSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

841

struct dml_mode_support_info_st support;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

358

dml_print("DML: MODE SUPPORT: Mode Supported : %s\n", mode_lib->ms.support.ModeSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

359

dml_print("DML: MODE SUPPORT: Scale Ratio And Taps : %s\n", mode_lib->ms.support.ScaleRatioAndTapsSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

360

dml_print("DML: MODE SUPPORT: Source Format Pixel And Scan : %s\n", mode_lib->ms.support.SourceFormatPixelAndScanSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

361

dml_print("DML: MODE SUPPORT: Viewport Size : %s\n", mode_lib->ms.support.ViewportSizeSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

362

dml_print("DML: MODE SUPPORT: Link Rate Does Not Match DP Version : %s\n", mode_lib->ms.support.LinkRateDoesNotMatchDPVersion == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

363

dml_print("DML: MODE SUPPORT: Link Rate For Multistream Not Indicated : %s\n", mode_lib->ms.support.LinkRateForMultistreamNotIndicated == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

364

dml_print("DML: MODE SUPPORT: BPP For Multi stream Not Indicated : %s\n", mode_lib->ms.support.BPPForMultistreamNotIndicated == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

365

dml_print("DML: MODE SUPPORT: Multistream With HDMI Or eDP : %s\n", mode_lib->ms.support.MultistreamWithHDMIOreDP == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

366

dml_print("DML: MODE SUPPORT: Exceeded Multistream Slots : %s\n", mode_lib->ms.support.ExceededMultistreamSlots == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

367

dml_print("DML: MODE SUPPORT: MSO Or ODM Split With Non DP Link : %s\n", mode_lib->ms.support.MSOOrODMSplitWithNonDPLink == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

368

dml_print("DML: MODE SUPPORT: Not Enough Lanes For MSO : %s\n", mode_lib->ms.support.NotEnoughLanesForMSO == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

369

dml_print("DML: MODE SUPPORT: LinkCapacitySupport : %s\n", mode_lib->ms.support.LinkCapacitySupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

370

dml_print("DML: MODE SUPPORT: P2IWith420 : %s\n", mode_lib->ms.support.P2IWith420 == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

371

dml_print("DML: MODE SUPPORT: DSCOnlyIfNecessaryWithBPP : %s\n", mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

372

dml_print("DML: MODE SUPPORT: DSC422NativeNotSupported : %s\n", mode_lib->ms.support.DSC422NativeNotSupported == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

373

dml_print("DML: MODE SUPPORT: MPCCombineMethodIncompatible : %s\n", mode_lib->ms.support.MPCCombineMethodIncompatible == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

374

dml_print("DML: MODE SUPPORT: ODMCombineTwoToOneSupportCheckOK : %s\n", mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

375

dml_print("DML: MODE SUPPORT: ODMCombineFourToOneSupportCheckOK : %s\n", mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

376

dml_print("DML: MODE SUPPORT: NotEnoughDSCUnits : %s\n", mode_lib->ms.support.NotEnoughDSCUnits == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

377

dml_print("DML: MODE SUPPORT: NotEnoughDSCSlices : %s\n", mode_lib->ms.support.NotEnoughDSCSlices == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

378

dml_print("DML: MODE SUPPORT: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe : %s\n", mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

379

dml_print("DML: MODE SUPPORT: InvalidCombinationOfMALLUseForPStateAndStaticScreen : %s\n", mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

380

dml_print("DML: MODE SUPPORT: DSCCLKRequiredMoreThanSupported : %s\n", mode_lib->ms.support.DSCCLKRequiredMoreThanSupported == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

381

dml_print("DML: MODE SUPPORT: PixelsPerLinePerDSCUnitSupport : %s\n", mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

382

dml_print("DML: MODE SUPPORT: DTBCLKRequiredMoreThanSupported : %s\n", mode_lib->ms.support.DTBCLKRequiredMoreThanSupported == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

383

dml_print("DML: MODE SUPPORT: InvalidCombinationOfMALLUseForPState : %s\n", mode_lib->ms.support.InvalidCombinationOfMALLUseForPState == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

384

dml_print("DML: MODE SUPPORT: ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified : %s\n", mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

385

dml_print("DML: MODE SUPPORT: ROB Support : %s\n", mode_lib->ms.support.ROBSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

386

dml_print("DML: MODE SUPPORT: DISPCLK DPPCLK Support : %s\n", mode_lib->ms.support.DISPCLK_DPPCLK_Support[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

387

dml_print("DML: MODE SUPPORT: Total Available Pipes Support : %s\n", mode_lib->ms.support.TotalAvailablePipesSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

388

dml_print("DML: MODE SUPPORT: Number Of OTG Support : %s\n", mode_lib->ms.support.NumberOfOTGSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

389

dml_print("DML: MODE SUPPORT: Number Of DP2p0 Support : %s\n", mode_lib->ms.support.NumberOfDP2p0Support == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

390

dml_print("DML: MODE SUPPORT: Writeback Latency Support : %s\n", mode_lib->ms.support.WritebackLatencySupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

391

dml_print("DML: MODE SUPPORT: Writeback Scale Ratio And Taps Support : %s\n", mode_lib->ms.support.WritebackScaleRatioAndTapsSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

392

dml_print("DML: MODE SUPPORT: Cursor Support : %s\n", mode_lib->ms.support.CursorSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

393

dml_print("DML: MODE SUPPORT: Pitch Support : %s\n", mode_lib->ms.support.PitchSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

394

dml_print("DML: MODE SUPPORT: Viewport Exceeds Surface : %s\n", mode_lib->ms.support.ViewportExceedsSurface == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

395

dml_print("DML: MODE SUPPORT: Prefetch Supported : %s\n", mode_lib->ms.support.PrefetchSupported[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

396

dml_print("DML: MODE SUPPORT: VActive Bandwith Support : %s\n", mode_lib->ms.support.VActiveBandwithSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

397

dml_print("DML: MODE SUPPORT: Dynamic Metadata Supported : %s\n", mode_lib->ms.support.DynamicMetadataSupported[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

398

dml_print("DML: MODE SUPPORT: Total Vertical Active Bandwidth Support : %s\n", mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

399

dml_print("DML: MODE SUPPORT: VRatio In Prefetch Supported : %s\n", mode_lib->ms.support.VRatioInPrefetchSupported[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

400

dml_print("DML: MODE SUPPORT: PTE Buffer Size Not Exceeded : %s\n", mode_lib->ms.support.PTEBufferSizeNotExceeded[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

401

dml_print("DML: MODE SUPPORT: DCC Meta Buffer Size Not Exceeded : %s\n", mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

402

dml_print("DML: MODE SUPPORT: Non supported DSC Input BPC : %s\n", mode_lib->ms.support.NonsupportedDSCInputBPC == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

403

dml_print("DML: MODE SUPPORT: Exceeded MALL Size : %s\n", mode_lib->ms.support.ExceededMALLSize == false ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

404

dml_print("DML: MODE SUPPORT: Host VM or Immediate Flip Supported : %s\n", ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !mode_lib->scratch.dml_core_mode_support_locals.ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j]) ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

407

dml_print("DML: MODE SUPPORT: USR Retraining Support : %s\n", (!mode_lib->ms.policy.USRRetrainingRequiredFinal || &mode_lib->ms.support.USRRetrainingSupport[j]) ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

411

void dml_print_dml_mode_support_info(const struct dml_mode_support_info_st *support, dml_bool_t fail_only)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

415

if (!fail_only || support->ModeIsSupported == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

416

dml_print("DML: support: ModeIsSupported = 0x%x\n", support->ModeIsSupported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

417

if (!fail_only || support->ImmediateFlipSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

418

dml_print("DML: support: ImmediateFlipSupport = 0x%x\n", support->ImmediateFlipSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

419

if (!fail_only || support->WritebackLatencySupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

420

dml_print("DML: support: WritebackLatencySupport = 0x%x\n", support->WritebackLatencySupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

421

if (!fail_only || support->ScaleRatioAndTapsSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

422

dml_print("DML: support: ScaleRatioAndTapsSupport = 0x%x\n", support->ScaleRatioAndTapsSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

423

if (!fail_only || support->SourceFormatPixelAndScanSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

424

dml_print("DML: support: SourceFormatPixelAndScanSupport = 0x%x\n", support->SourceFormatPixelAndScanSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

425

if (!fail_only || support->MPCCombineMethodIncompatible == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

426

dml_print("DML: support: MPCCombineMethodIncompatible = 0x%x\n", support->MPCCombineMethodIncompatible);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

427

if (!fail_only || support->P2IWith420 == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

428

dml_print("DML: support: P2IWith420 = 0x%x\n", support->P2IWith420);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

429

if (!fail_only || support->DSCOnlyIfNecessaryWithBPP == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

430

dml_print("DML: support: DSCOnlyIfNecessaryWithBPP = 0x%x\n", support->DSCOnlyIfNecessaryWithBPP);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

431

if (!fail_only || support->DSC422NativeNotSupported == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

432

dml_print("DML: support: DSC422NativeNotSupported = 0x%x\n", support->DSC422NativeNotSupported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

433

if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

434

dml_print("DML: support: LinkRateDoesNotMatchDPVersion = 0x%x\n", support->LinkRateDoesNotMatchDPVersion);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

435

if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

436

dml_print("DML: support: LinkRateForMultistreamNotIndicated = 0x%x\n", support->LinkRateForMultistreamNotIndicated);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

437

if (!fail_only || support->BPPForMultistreamNotIndicated == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

438

dml_print("DML: support: BPPForMultistreamNotIndicated = 0x%x\n", support->BPPForMultistreamNotIndicated);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

439

if (!fail_only || support->MultistreamWithHDMIOreDP == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

440

dml_print("DML: support: MultistreamWithHDMIOreDP = 0x%x\n", support->MultistreamWithHDMIOreDP);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

441

if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

442

dml_print("DML: support: MSOOrODMSplitWithNonDPLink = 0x%x\n", support->MSOOrODMSplitWithNonDPLink);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

443

if (!fail_only || support->NotEnoughLanesForMSO == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

444

dml_print("DML: support: NotEnoughLanesForMSO = 0x%x\n", support->NotEnoughLanesForMSO);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

445

if (!fail_only || support->NumberOfOTGSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

446

dml_print("DML: support: NumberOfOTGSupport = 0x%x\n", support->NumberOfOTGSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

447

if (!fail_only || support->NumberOfDP2p0Support == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

448

dml_print("DML: support: NumberOfDP2p0Support = 0x%x\n", support->NumberOfDP2p0Support);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

449

if (!fail_only || support->NonsupportedDSCInputBPC == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

450

dml_print("DML: support: NonsupportedDSCInputBPC = 0x%x\n", support->NonsupportedDSCInputBPC);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

451

if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

452

dml_print("DML: support: WritebackScaleRatioAndTapsSupport = 0x%x\n", support->WritebackScaleRatioAndTapsSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

453

if (!fail_only || support->CursorSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

454

dml_print("DML: support: CursorSupport = 0x%x\n", support->CursorSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

455

if (!fail_only || support->PitchSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

456

dml_print("DML: support: PitchSupport = 0x%x\n", support->PitchSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

457

if (!fail_only || support->ViewportExceedsSurface == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

458

dml_print("DML: support: ViewportExceedsSurface = 0x%x\n", support->ViewportExceedsSurface);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

459

if (!fail_only || support->ExceededMALLSize == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

460

dml_print("DML: support: ExceededMALLSize = 0x%x\n", support->ExceededMALLSize);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

461

if (!fail_only || support->EnoughWritebackUnits == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

462

dml_print("DML: support: EnoughWritebackUnits = 0x%x\n", support->EnoughWritebackUnits);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

463

if (!fail_only || support->ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

464

dml_print("DML: support: ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = 0x%x\n", support->ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

465

if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

466

dml_print("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = 0x%x\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

467

if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

468

dml_print("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = 0x%x\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

469

if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

470

dml_print("DML: support: InvalidCombinationOfMALLUseForPState = 0x%x\n", support->InvalidCombinationOfMALLUseForPState);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

472

if (!fail_only || support->ExceededMultistreamSlots == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

473

dml_print("DML: support: ExceededMultistreamSlots = 0x%x\n", support->ExceededMultistreamSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

474

if (!fail_only || support->ODMCombineTwoToOneSupportCheckOK == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

475

dml_print("DML: support: ODMCombineTwoToOneSupportCheckOK = 0x%x\n", support->ODMCombineTwoToOneSupportCheckOK);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

476

if (!fail_only || support->ODMCombineFourToOneSupportCheckOK == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

477

dml_print("DML: support: ODMCombineFourToOneSupportCheckOK = 0x%x\n", support->ODMCombineFourToOneSupportCheckOK);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

478

if (!fail_only || support->NotEnoughDSCUnits == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

479

dml_print("DML: support: NotEnoughDSCUnits = 0x%x\n", support->NotEnoughDSCUnits);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

480

if (!fail_only || support->NotEnoughDSCSlices == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

481

dml_print("DML: support: NotEnoughDSCSlices = 0x%x\n", support->NotEnoughDSCSlices);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

482

if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

483

dml_print("DML: support: PixelsPerLinePerDSCUnitSupport = 0x%x\n", support->PixelsPerLinePerDSCUnitSupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

484

if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

485

dml_print("DML: support: DSCCLKRequiredMoreThanSupported = 0x%x\n", support->DSCCLKRequiredMoreThanSupported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

486

if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

487

dml_print("DML: support: DTBCLKRequiredMoreThanSupported = 0x%x\n", support->DTBCLKRequiredMoreThanSupported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

488

if (!fail_only || support->LinkCapacitySupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

489

dml_print("DML: support: LinkCapacitySupport = 0x%x\n", support->LinkCapacitySupport);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

492

if (!fail_only || support->DRAMClockChangeSupport[j] == dml_dram_clock_change_unsupported)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

493

dml_print("DML: support: combine=%d, DRAMClockChangeSupport = %d\n", j, support->DRAMClockChangeSupport[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

494

if (!fail_only || support->FCLKChangeSupport[j] == dml_fclock_change_unsupported)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

495

dml_print("DML: support: combine=%d, FCLKChangeSupport = %d\n", j, support->FCLKChangeSupport[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

496

if (!fail_only || support->ROBSupport[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

497

dml_print("DML: support: combine=%d, ROBSupport = %d\n", j, support->ROBSupport[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

498

if (!fail_only || support->PTEBufferSizeNotExceeded[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

499

dml_print("DML: support: combine=%d, PTEBufferSizeNotExceeded = %d\n", j, support->PTEBufferSizeNotExceeded[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

500

if (!fail_only || support->DCCMetaBufferSizeNotExceeded[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

501

dml_print("DML: support: combine=%d, DCCMetaBufferSizeNotExceeded = %d\n", j, support->DCCMetaBufferSizeNotExceeded[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

502

if (!fail_only || support->TotalVerticalActiveBandwidthSupport[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

503

dml_print("DML: support: combine=%d, TotalVerticalActiveBandwidthSupport = %d\n", j, support->TotalVerticalActiveBandwidthSupport[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

504

if (!fail_only || support->USRRetrainingSupport[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

505

dml_print("DML: support: combine=%d, USRRetrainingSupport = %d\n", j, support->USRRetrainingSupport[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

506

if (!fail_only || support->VActiveBandwithSupport[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

507

dml_print("DML: support: combine=%d, VActiveBandwithSupport = %d\n", j, support->VActiveBandwithSupport[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

508

if (!fail_only || support->PrefetchSupported[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

509

dml_print("DML: support: combine=%d, PrefetchSupported = %d\n", j, support->PrefetchSupported[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

510

if (!fail_only || support->DynamicMetadataSupported[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

511

dml_print("DML: support: combine=%d, DynamicMetadataSupported = %d\n", j, support->DynamicMetadataSupported[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

512

if (!fail_only || support->VRatioInPrefetchSupported[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

513

dml_print("DML: support: combine=%d, VRatioInPrefetchSupported = %d\n", j, support->VRatioInPrefetchSupported[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

514

if (!fail_only || support->DISPCLK_DPPCLK_Support[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

515

dml_print("DML: support: combine=%d, DISPCLK_DPPCLK_Support = %d\n", j, support->DISPCLK_DPPCLK_Support[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

516

if (!fail_only || support->TotalAvailablePipesSupport[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

517

dml_print("DML: support: combine=%d, TotalAvailablePipesSupport = %d\n", j, support->TotalAvailablePipesSupport[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

518

if (!fail_only || support->ModeSupport[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

519

dml_print("DML: support: combine=%d, ModeSupport = %d\n", j, support->ModeSupport[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

520

if (!fail_only || support->ViewportSizeSupport[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

521

dml_print("DML: support: combine=%d, ViewportSizeSupport = %d\n", j, support->ViewportSizeSupport[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

522

if (!fail_only || support->ImmediateFlipSupportedForState[j] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

523

dml_print("DML: support: combine=%d, ImmediateFlipSupportedForState = %d\n", j, support->ImmediateFlipSupportedForState[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

60

__DML_DLL_EXPORT__ void dml_print_dml_mode_support_info(const struct dml_mode_support_info_st *support, dml_bool_t fail_only);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

100

DML_LOG_VERBOSE("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support->InvalidCombinationOfMALLUseForPState);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

101

if (!fail_only || support->ROBSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

102

DML_LOG_VERBOSE("DML: support: ROBSupport = %d\n", support->ROBSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

103

if (!fail_only || support->OutstandingRequestsSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

104

DML_LOG_VERBOSE("DML: support: OutstandingRequestsSupport = %d\n", support->OutstandingRequestsSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

105

if (!fail_only || support->OutstandingRequestsUrgencyAvoidance == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

106

DML_LOG_VERBOSE("DML: support: OutstandingRequestsUrgencyAvoidance = %d\n", support->OutstandingRequestsUrgencyAvoidance);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

107

if (!fail_only || support->DISPCLK_DPPCLK_Support == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

108

DML_LOG_VERBOSE("DML: support: DISPCLK_DPPCLK_Support = %d\n", support->DISPCLK_DPPCLK_Support);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

109

if (!fail_only || support->TotalAvailablePipesSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

110

DML_LOG_VERBOSE("DML: support: TotalAvailablePipesSupport = %d\n", support->TotalAvailablePipesSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

111

if (!fail_only || support->NumberOfOTGSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

112

DML_LOG_VERBOSE("DML: support: NumberOfOTGSupport = %d\n", support->NumberOfOTGSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

113

if (!fail_only || support->NumberOfHDMIFRLSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

114

DML_LOG_VERBOSE("DML: support: NumberOfHDMIFRLSupport = %d\n", support->NumberOfHDMIFRLSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

115

if (!fail_only || support->NumberOfDP2p0Support == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

116

DML_LOG_VERBOSE("DML: support: NumberOfDP2p0Support = %d\n", support->NumberOfDP2p0Support);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

117

if (!fail_only || support->EnoughWritebackUnits == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

118

DML_LOG_VERBOSE("DML: support: EnoughWritebackUnits = %d\n", support->EnoughWritebackUnits);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

119

if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

120

DML_LOG_VERBOSE("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support->WritebackScaleRatioAndTapsSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

121

if (!fail_only || support->WritebackLatencySupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

122

DML_LOG_VERBOSE("DML: support: WritebackLatencySupport = %d\n", support->WritebackLatencySupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

123

if (!fail_only || support->CursorSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

124

DML_LOG_VERBOSE("DML: support: CursorSupport = %d\n", support->CursorSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

125

if (!fail_only || support->PitchSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

126

DML_LOG_VERBOSE("DML: support: PitchSupport = %d\n", support->PitchSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

127

if (!fail_only || support->ViewportExceedsSurface == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

128

DML_LOG_VERBOSE("DML: support: ViewportExceedsSurface = %d\n", support->ViewportExceedsSurface);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

129

if (!fail_only || support->PrefetchSupported == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12977

out->informative.mode_support_info.ModeIsSupported = mode_lib->ms.support.ModeSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12978

out->informative.mode_support_info.ImmediateFlipSupport = mode_lib->ms.support.ImmediateFlipSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12979

out->informative.mode_support_info.WritebackLatencySupport = mode_lib->ms.support.WritebackLatencySupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12980

out->informative.mode_support_info.ScaleRatioAndTapsSupport = mode_lib->ms.support.ScaleRatioAndTapsSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12981

out->informative.mode_support_info.SourceFormatPixelAndScanSupport = mode_lib->ms.support.SourceFormatPixelAndScanSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12982

out->informative.mode_support_info.P2IWith420 = mode_lib->ms.support.P2IWith420;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12984

out->informative.mode_support_info.DSC422NativeNotSupported = mode_lib->ms.support.DSC422NativeNotSupported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12985

out->informative.mode_support_info.LinkRateDoesNotMatchDPVersion = mode_lib->ms.support.LinkRateDoesNotMatchDPVersion;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12986

out->informative.mode_support_info.LinkRateForMultistreamNotIndicated = mode_lib->ms.support.LinkRateForMultistreamNotIndicated;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12987

out->informative.mode_support_info.BPPForMultistreamNotIndicated = mode_lib->ms.support.BPPForMultistreamNotIndicated;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12988

out->informative.mode_support_info.MultistreamWithHDMIOreDP = mode_lib->ms.support.MultistreamWithHDMIOreDP;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12989

out->informative.mode_support_info.MSOOrODMSplitWithNonDPLink = mode_lib->ms.support.MSOOrODMSplitWithNonDPLink;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12990

out->informative.mode_support_info.NotEnoughLanesForMSO = mode_lib->ms.support.NotEnoughLanesForMSO;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12991

out->informative.mode_support_info.NumberOfOTGSupport = mode_lib->ms.support.NumberOfOTGSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12992

out->informative.mode_support_info.NumberOfHDMIFRLSupport = mode_lib->ms.support.NumberOfHDMIFRLSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12993

out->informative.mode_support_info.NumberOfDP2p0Support = mode_lib->ms.support.NumberOfDP2p0Support;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12994

out->informative.mode_support_info.WritebackScaleRatioAndTapsSupport = mode_lib->ms.support.WritebackScaleRatioAndTapsSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12995

out->informative.mode_support_info.CursorSupport = mode_lib->ms.support.CursorSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12996

out->informative.mode_support_info.PitchSupport = mode_lib->ms.support.PitchSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12997

out->informative.mode_support_info.ViewportExceedsSurface = mode_lib->ms.support.ViewportExceedsSurface;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12999

out->informative.mode_support_info.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

130

DML_LOG_VERBOSE("DML: support: PrefetchSupported = %d\n", support->PrefetchSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13000

out->informative.mode_support_info.InvalidCombinationOfMALLUseForPStateAndStaticScreen = mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13001

out->informative.mode_support_info.InvalidCombinationOfMALLUseForPState = mode_lib->ms.support.InvalidCombinationOfMALLUseForPState;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13002

out->informative.mode_support_info.ExceededMALLSize = mode_lib->ms.support.ExceededMALLSize;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13003

out->informative.mode_support_info.EnoughWritebackUnits = mode_lib->ms.support.EnoughWritebackUnits;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13004

out->informative.mode_support_info.temp_read_or_ppt_support = mode_lib->ms.support.temp_read_or_ppt_support;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13005

out->informative.mode_support_info.g6_temp_read_support = mode_lib->ms.support.g6_temp_read_support;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13007

out->informative.mode_support_info.ExceededMultistreamSlots = mode_lib->ms.support.ExceededMultistreamSlots;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13008

out->informative.mode_support_info.NotEnoughDSCUnits = mode_lib->ms.support.NotEnoughDSCUnits;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13009

out->informative.mode_support_info.NotEnoughDSCSlices = mode_lib->ms.support.NotEnoughDSCSlices;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13010

out->informative.mode_support_info.PixelsPerLinePerDSCUnitSupport = mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13011

out->informative.mode_support_info.DSCCLKRequiredMoreThanSupported = mode_lib->ms.support.DSCCLKRequiredMoreThanSupported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13012

out->informative.mode_support_info.DTBCLKRequiredMoreThanSupported = mode_lib->ms.support.DTBCLKRequiredMoreThanSupported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13013

out->informative.mode_support_info.LinkCapacitySupport = mode_lib->ms.support.LinkCapacitySupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13015

out->informative.mode_support_info.ROBSupport = mode_lib->ms.support.ROBSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13016

out->informative.mode_support_info.OutstandingRequestsSupport = mode_lib->ms.support.OutstandingRequestsSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13017

out->informative.mode_support_info.OutstandingRequestsUrgencyAvoidance = mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13018

out->informative.mode_support_info.PTEBufferSizeNotExceeded = mode_lib->ms.support.PTEBufferSizeNotExceeded;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13019

out->informative.mode_support_info.DCCMetaBufferSizeNotExceeded = mode_lib->ms.support.DCCMetaBufferSizeNotExceeded;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13021

out->informative.mode_support_info.TotalVerticalActiveBandwidthSupport = mode_lib->ms.support.AvgBandwidthSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13022

out->informative.mode_support_info.VActiveBandwidthSupport = mode_lib->ms.support.UrgVactiveBandwidthSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13023

out->informative.mode_support_info.USRRetrainingSupport = mode_lib->ms.support.USRRetrainingSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13025

out->informative.mode_support_info.PrefetchSupported = mode_lib->ms.support.PrefetchSupported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13026

out->informative.mode_support_info.DynamicMetadataSupported = mode_lib->ms.support.DynamicMetadataSupported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13027

out->informative.mode_support_info.VRatioInPrefetchSupported = mode_lib->ms.support.VRatioInPrefetchSupported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13028

out->informative.mode_support_info.DISPCLK_DPPCLK_Support = mode_lib->ms.support.DISPCLK_DPPCLK_Support;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13029

out->informative.mode_support_info.TotalAvailablePipesSupport = mode_lib->ms.support.TotalAvailablePipesSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13030

out->informative.mode_support_info.ViewportSizeSupport = mode_lib->ms.support.ViewportSizeSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13034

out->informative.mode_support_info.FCLKChangeSupport[k] = mode_lib->ms.support.FCLKChangeSupport[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13035

out->informative.mode_support_info.MPCCombineEnable[k] = mode_lib->ms.support.MPCCombineEnable[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13036

out->informative.mode_support_info.ODMMode[k] = mode_lib->ms.support.ODMMode[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13037

out->informative.mode_support_info.DPPPerSurface[k] = mode_lib->ms.support.DPPPerSurface[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13038

out->informative.mode_support_info.DSCEnabled[k] = mode_lib->ms.support.DSCEnabled[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13039

out->informative.mode_support_info.FECEnabled[k] = mode_lib->ms.support.FECEnabled[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13040

out->informative.mode_support_info.NumberOfDSCSlices[k] = mode_lib->ms.support.NumberOfDSCSlices[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13041

out->informative.mode_support_info.OutputBpp[k] = mode_lib->ms.support.OutputBpp[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13043

if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_unknown)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13045

else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_dp)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13047

else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_edp)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13049

else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_dp2p0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13051

else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_hdmi)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13053

else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_hdmifrl)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13056

if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_unknown)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13058

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13060

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr2)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13062

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr3)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13064

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr10)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13066

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr13p5)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13068

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr20)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13070

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_3x3)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13072

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_6x3)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13074

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_6x4)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13076

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_8x4)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13078

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_10x4)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13080

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_12x4)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13082

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_16x4)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13084

else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_20x4)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13087

out->informative.mode_support_info.AlignedYPitch[k] = mode_lib->ms.support.AlignedYPitch[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13088

out->informative.mode_support_info.AlignedCPitch[k] = mode_lib->ms.support.AlignedCPitch[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

131

if (!fail_only || support->EnoughUrgentLatencyHidingSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

132

DML_LOG_VERBOSE("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support->EnoughUrgentLatencyHidingSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

133

if (!fail_only || support->AvgBandwidthSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13307

/ mode_lib->ms.support.non_urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) >= out->informative.qos.max_non_urgent_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

134

DML_LOG_VERBOSE("DML: support: AvgBandwidthSupport = %d\n", support->AvgBandwidthSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

135

if (!fail_only || support->DynamicMetadataSupported == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

136

DML_LOG_VERBOSE("DML: support: DynamicMetadataSupported = %d\n", support->DynamicMetadataSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

137

if (!fail_only || support->VRatioInPrefetchSupported == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

138

DML_LOG_VERBOSE("DML: support: VRatioInPrefetchSupported = %d\n", support->VRatioInPrefetchSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

139

if (!fail_only || support->PTEBufferSizeNotExceeded == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

140

DML_LOG_VERBOSE("DML: support: PTEBufferSizeNotExceeded = %d\n", support->PTEBufferSizeNotExceeded);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

141

if (!fail_only || support->DCCMetaBufferSizeNotExceeded == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

142

DML_LOG_VERBOSE("DML: support: DCCMetaBufferSizeNotExceeded = %d\n", support->DCCMetaBufferSizeNotExceeded);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

143

if (!fail_only || support->ExceededMALLSize == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

144

DML_LOG_VERBOSE("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

145

if (!fail_only || support->g6_temp_read_support == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

146

DML_LOG_VERBOSE("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

147

if (!fail_only || support->ImmediateFlipSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

148

DML_LOG_VERBOSE("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

149

if (!fail_only || support->LinkCapacitySupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

150

DML_LOG_VERBOSE("DML: support: LinkCapacitySupport = %d\n", support->LinkCapacitySupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

152

if (!fail_only || support->ModeSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

153

DML_LOG_VERBOSE("DML: support: ModeSupport = %d\n", support->ModeSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

337

dml_get_var_func(sys_active_avg_bw_required_sdp, double, mode_lib->ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

338

dml_get_var_func(sys_active_avg_bw_required_dram, double, mode_lib->ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

340

dml_get_var_func(svp_prefetch_avg_bw_required_sdp, double, mode_lib->ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

341

dml_get_var_func(svp_prefetch_avg_bw_required_dram, double, mode_lib->ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

358

dml_get_var_func(max_urgent_latency_us, double, mode_lib->ms.support.max_urgent_latency_us);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

359

dml_get_var_func(max_non_urgent_latency_us, double, mode_lib->ms.support.max_non_urgent_latency_us);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

360

dml_get_var_func(avg_non_urgent_latency_us, double, mode_lib->ms.support.avg_non_urgent_latency_us);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

361

dml_get_var_func(avg_urgent_latency_us, double, mode_lib->ms.support.avg_urgent_latency_us);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

55

static void dml2_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

59

if (!fail_only || support->ScaleRatioAndTapsSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

60

DML_LOG_VERBOSE("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

61

if (!fail_only || support->SourceFormatPixelAndScanSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

62

DML_LOG_VERBOSE("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndScanSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

63

if (!fail_only || support->ViewportSizeSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

64

DML_LOG_VERBOSE("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

65

if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

66

DML_LOG_VERBOSE("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPVersion);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

67

if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

68

DML_LOG_VERBOSE("DML: support: LinkRateForMultistreamNotIndicated = %d\n", support->LinkRateForMultistreamNotIndicated);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

69

if (!fail_only || support->BPPForMultistreamNotIndicated == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

70

DML_LOG_VERBOSE("DML: support: BPPForMultistreamNotIndicated = %d\n", support->BPPForMultistreamNotIndicated);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

71

if (!fail_only || support->MultistreamWithHDMIOreDP == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

72

DML_LOG_VERBOSE("DML: support: MultistreamWithHDMIOreDP = %d\n", support->MultistreamWithHDMIOreDP);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

73

if (!fail_only || support->ExceededMultistreamSlots == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7311

mode_lib->ms.support.urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_sys_active],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7312

mode_lib->ms.support.urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_sys_active]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7342

min_return_bw_for_latency = mode_lib->ms.support.urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_sys_active];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7368

mode_lib->ms.support.request_size_bytes_luma,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7369

mode_lib->ms.support.request_size_bytes_chroma,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7386

mode_lib->ms.support.PrefetchSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

74

DML_LOG_VERBOSE("DML: support: ExceededMultistreamSlots = %d\n", support->ExceededMultistreamSlots);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

75

if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7534

mode_lib->ms.support.PrefetchSupported &= !mode_lib->ms.NoTimeForPrefetch[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7566

mode_lib->ms.support.PrefetchSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7575

mode_lib->ms.support.DynamicMetadataSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7578

mode_lib->ms.support.DynamicMetadataSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7582

mode_lib->ms.support.VRatioInPrefetchSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7586

mode_lib->ms.support.VRatioInPrefetchSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7589

DML_LOG_VERBOSE("DML::%s: VRatioInPrefetchSupported = %u\n", __func__, mode_lib->ms.support.VRatioInPrefetchSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7593

mode_lib->ms.support.PrefetchSupported &= mode_lib->ms.support.VRatioInPrefetchSupported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7599

if (mode_lib->ms.support.PrefetchSupported) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

76

DML_LOG_VERBOSE("DML: support: MSOOrODMSplitWithNonDPLink = %d\n", support->MSOOrODMSplitWithNonDPLink);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7632

calculate_peak_bandwidth_params->urg_vactive_bandwidth_required = mode_lib->ms.support.urg_vactive_bandwidth_required;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7633

calculate_peak_bandwidth_params->urg_bandwidth_required = mode_lib->ms.support.urg_bandwidth_required;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7634

calculate_peak_bandwidth_params->urg_bandwidth_required_qual = mode_lib->ms.support.urg_bandwidth_required_qual;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7635

calculate_peak_bandwidth_params->non_urg_bandwidth_required = mode_lib->ms.support.non_urg_bandwidth_required;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7679

&mode_lib->ms.support.UrgVactiveBandwidthSupport,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7680

&mode_lib->ms.support.PrefetchBandwidthSupported,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7683

mode_lib->ms.support.non_urg_bandwidth_required,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7684

mode_lib->ms.support.urg_vactive_bandwidth_required,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7685

mode_lib->ms.support.urg_bandwidth_required,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7686

mode_lib->ms.support.urg_bandwidth_available);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7688

mode_lib->ms.support.PrefetchSupported &= mode_lib->ms.support.PrefetchBandwidthSupported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7689

DML_LOG_VERBOSE("DML::%s: PrefetchBandwidthSupported=%0d\n", __func__, mode_lib->ms.support.PrefetchBandwidthSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7693

mode_lib->ms.support.PrefetchSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7699

if (mode_lib->ms.support.PrefetchSupported && mode_lib->ms.num_active_planes > 1 && s->recalc_prefetch_done == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

77

if (!fail_only || support->NotEnoughLanesForMSO == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7717

CheckGlobalPrefetchAdmissibility_params->estimated_urg_bandwidth_required_mbps = mode_lib->ms.support.urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7729

mode_lib->ms.support.PrefetchSupported = CheckGlobalPrefetchAdmissibility(&mode_lib->scratch, CheckGlobalPrefetchAdmissibility_params);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7739

if (mode_lib->ms.support.PrefetchSupported == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7743

mode_lib->ms.support.urg_bandwidth_required_qual, // no flip

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7744

mode_lib->ms.support.urg_bandwidth_available);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

78

DML_LOG_VERBOSE("DML: support: NotEnoughLanesForMSO = %d\n", support->NotEnoughLanesForMSO);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7800

calculate_peak_bandwidth_params->urg_bandwidth_required = mode_lib->ms.support.urg_bandwidth_required_flip;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7802

calculate_peak_bandwidth_params->non_urg_bandwidth_required = mode_lib->ms.support.non_urg_bandwidth_required_flip;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7843

&mode_lib->ms.support.ImmediateFlipSupport,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7846

mode_lib->ms.support.urg_bandwidth_required_flip,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7847

mode_lib->ms.support.non_urg_bandwidth_required_flip,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7848

mode_lib->ms.support.urg_bandwidth_available);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7852

mode_lib->ms.support.ImmediateFlipSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7856

mode_lib->ms.support.ImmediateFlipSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

79

if (!fail_only || support->P2IWith420 == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7907

CalculateWatermarks_params->Watermark = &mode_lib->ms.support.watermarks; // Watermarks *Watermark

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7908

CalculateWatermarks_params->DRAMClockChangeSupport = mode_lib->ms.support.DRAMClockChangeSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7909

CalculateWatermarks_params->global_dram_clock_change_supported = &mode_lib->ms.support.global_dram_clock_change_supported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7912

CalculateWatermarks_params->FCLKChangeSupport = mode_lib->ms.support.FCLKChangeSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7913

CalculateWatermarks_params->global_fclk_change_supported = &mode_lib->ms.support.global_fclk_change_supported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7915

CalculateWatermarks_params->USRRetrainingSupport = &mode_lib->ms.support.USRRetrainingSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7916

CalculateWatermarks_params->g6_temp_read_support = &mode_lib->ms.support.g6_temp_read_support;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7922

calculate_pstate_keepout_dst_lines(display_cfg, &mode_lib->ms.support.watermarks, s->dummy_integer_array[0]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

80

DML_LOG_VERBOSE("DML: support: P2IWith420 = %d\n", support->P2IWith420);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8005

mode_lib->ms.support.ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8014

mode_lib->ms.support.ScaleRatioAndTapsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8030

mode_lib->ms.support.ScaleRatioAndTapsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8035

mode_lib->ms.support.SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8038

mode_lib->ms.support.SourceFormatPixelAndScanSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

81

if (!fail_only || support->DSC422NativeNotSupported == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8112

mode_lib->ms.support.WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8116

mode_lib->ms.support.WritebackLatencySupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8122

mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8134

mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8137

mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

82

DML_LOG_VERBOSE("DML: support: DSC422NativeNotSupported = %d\n", support->DSC422NativeNotSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8218

mode_lib->ms.support.CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8222

mode_lib->ms.support.CursorSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8227

mode_lib->ms.support.PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8236

mode_lib->ms.support.AlignedYPitch[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.plane0.pitch, display_cfg->plane_descriptors[k].surface.plane0.width), alignment_l);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8242

mode_lib->ms.support.AlignedCPitch[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.plane1.pitch, display_cfg->plane_descriptors[k].surface.plane1.width), alignment_c);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8244

mode_lib->ms.support.AlignedCPitch[k] = display_cfg->plane_descriptors[k].surface.plane1.pitch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8247

if (mode_lib->ms.support.AlignedYPitch[k] > display_cfg->plane_descriptors[k].surface.plane0.pitch ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8248

mode_lib->ms.support.AlignedCPitch[k] > display_cfg->plane_descriptors[k].surface.plane1.pitch) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8249

mode_lib->ms.support.PitchSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8251

DML_LOG_VERBOSE("DML::%s: k=%u AlignedYPitch = %d\n", __func__, k, mode_lib->ms.support.AlignedYPitch[k]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8253

DML_LOG_VERBOSE("DML::%s: k=%u AlignedCPitch = %d\n", __func__, k, mode_lib->ms.support.AlignedCPitch[k]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8255

DML_LOG_VERBOSE("DML::%s: k=%u PitchSupport = %d\n", __func__, k, mode_lib->ms.support.PitchSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8261

mode_lib->ms.support.AlignedDCCMetaPitchY[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8264

if (mode_lib->ms.support.AlignedDCCMetaPitchY[k] > display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8265

mode_lib->ms.support.PitchSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8268

mode_lib->ms.support.AlignedDCCMetaPitchC[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8271

if (mode_lib->ms.support.AlignedDCCMetaPitchC[k] > display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8272

mode_lib->ms.support.PitchSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8275

mode_lib->ms.support.AlignedDCCMetaPitchY[k] = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8276

mode_lib->ms.support.AlignedDCCMetaPitchC[k] = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8280

mode_lib->ms.support.ViewportExceedsSurface = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8285

mode_lib->ms.support.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8291

DML_LOG_VERBOSE("DML::%s: k=%u ViewportExceedsSurface = %d\n", __func__, k, mode_lib->ms.support.ViewportExceedsSurface);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8297

mode_lib->ms.support.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

83

if (!fail_only || support->DSCSlicesODMModeSupported == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8361

mode_lib->ms.support.TotalAvailablePipesSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8369

mode_lib->ms.support.NumberOfDSCSlices[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8372

mode_lib->ms.support.NumberOfDSCSlices[k] = (unsigned int)(math_ceil2(s->PixelClockBackEnd[k] / 600, 4));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8374

mode_lib->ms.support.NumberOfDSCSlices[k] = 8;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8376

mode_lib->ms.support.NumberOfDSCSlices[k] = 4;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8378

mode_lib->ms.support.NumberOfDSCSlices[k] = 2;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8380

mode_lib->ms.support.NumberOfDSCSlices[k] = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8384

mode_lib->ms.support.NumberOfDSCSlices[k] = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8398

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

84

DML_LOG_VERBOSE("DML: support: DSCSlicesODMModeSupported = %d\n", support->DSCSlicesODMModeSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8417

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8438

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8463

mode_lib->ms.support.TotalAvailablePipesSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8469

mode_lib->ms.support.TotalAvailablePipesSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8478

mode_lib->ms.support.DSCSlicesODMModeSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8483

mode_lib->ms.support.DSCSlicesODMModeSupported = ((mode_lib->ms.support.NumberOfDSCSlices[k] % 2) == 0);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8485

mode_lib->ms.support.DSCSlicesODMModeSupported = (mode_lib->ms.support.NumberOfDSCSlices[k] == 12);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8487

mode_lib->ms.support.DSCSlicesODMModeSupported = ((mode_lib->ms.support.NumberOfDSCSlices[k] % 4) == 0);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8489

if (!mode_lib->ms.support.DSCSlicesODMModeSupported) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8498

mode_lib->ms.support.NumberOfDSCSlices[k] = 2 * (unsigned int)math_ceil2(mode_lib->ms.support.NumberOfDSCSlices[k] / 2.0, 1.0);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

85

if (!fail_only || support->NotEnoughDSCUnits == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8500

mode_lib->ms.support.NumberOfDSCSlices[k] = 12;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8502

mode_lib->ms.support.NumberOfDSCSlices[k] = 4 * (unsigned int)math_ceil2(mode_lib->ms.support.NumberOfDSCSlices[k] / 4.0, 1.0);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8506

mode_lib->ms.support.NumberOfDSCSlices[k] = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8510

mode_lib->ms.support.incorrect_imall_usage = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8513

mode_lib->ms.support.incorrect_imall_usage = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8552

mode_lib->ms.support.TotalAvailablePipesSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8590

mode_lib->ms.support.DISPCLK_DPPCLK_Support = !((mode_lib->ms.RequiredDISPCLK > mode_lib->ms.max_dispclk_freq_mhz) || (mode_lib->ms.GlobalDPPCLK > mode_lib->ms.max_dppclk_freq_mhz));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

86

DML_LOG_VERBOSE("DML: support: NotEnoughDSCUnits = %d\n", support->NotEnoughDSCUnits);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8623

mode_lib->ms.support.EnoughWritebackUnits = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8625

mode_lib->ms.support.EnoughWritebackUnits = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8627

mode_lib->ms.support.NumberOfOTGSupport = (s->TotalNumberOfActiveOTG <= (unsigned int)mode_lib->ip.max_num_otg);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8628

mode_lib->ms.support.NumberOfHDMIFRLSupport = (s->TotalNumberOfActiveHDMIFRL <= (unsigned int)mode_lib->ip.max_num_hdmi_frl_outputs);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8629

mode_lib->ms.support.NumberOfDP2p0Support = (s->TotalNumberOfActiveDP2p0 <= (unsigned int)mode_lib->ip.max_num_dp2p0_streams && s->TotalNumberOfActiveDP2p0Outputs <= (unsigned int)mode_lib->ip.max_num_dp2p0_outputs);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8632

mode_lib->ms.support.ExceededMultistreamSlots = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8633

mode_lib->ms.support.LinkCapacitySupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8638

mode_lib->ms.support.LinkCapacitySupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8642

mode_lib->ms.support.P2IWith420 = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8643

mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8644

mode_lib->ms.support.DSC422NativeNotSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8645

mode_lib->ms.support.LinkRateDoesNotMatchDPVersion = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8646

mode_lib->ms.support.LinkRateForMultistreamNotIndicated = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8647

mode_lib->ms.support.BPPForMultistreamNotIndicated = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8648

mode_lib->ms.support.MultistreamWithHDMIOreDP = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8649

mode_lib->ms.support.MSOOrODMSplitWithNonDPLink = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8650

mode_lib->ms.support.NotEnoughLanesForMSO = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8656

mode_lib->ms.support.P2IWith420 = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8659

mode_lib->ms.support.DSC422NativeNotSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8667

mode_lib->ms.support.LinkRateDoesNotMatchDPVersion = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8694

mode_lib->ms.support.MSOOrODMSplitWithNonDPLink = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8698

mode_lib->ms.support.NotEnoughLanesForMSO = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

87

if (!fail_only || support->NotEnoughDSCSlices == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8702

mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8711

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8718

mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8730

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8760

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8767

DML_LOG_VERBOSE("DML::%s: k=%u, DSCCLKRequiredMoreThanSupported = %u\n", __func__, k, mode_lib->ms.support.DSCCLKRequiredMoreThanSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8774

mode_lib->ms.support.NotEnoughDSCSlices = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8776

mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8791

mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8794

if (mode_lib->ms.support.NumberOfDSCSlices[k] > 4 * s->NumDSCUnitRequired)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8795

mode_lib->ms.support.NotEnoughDSCSlices = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

88

DML_LOG_VERBOSE("DML: support: NotEnoughDSCSlices = %d\n", support->NotEnoughDSCSlices);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8800

mode_lib->ms.support.NotEnoughDSCUnits = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8802

mode_lib->ms.support.NotEnoughDSCUnits = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8813

mode_lib->ms.support.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8834

CalculateSwathAndDETConfiguration_params->request_size_bytes_luma = mode_lib->ms.support.request_size_bytes_luma;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8835

CalculateSwathAndDETConfiguration_params->request_size_bytes_chroma = mode_lib->ms.support.request_size_bytes_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8844

CalculateSwathAndDETConfiguration_params->ViewportSizeSupport = &mode_lib->ms.support.ViewportSizeSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8851

mode_lib->ms.support.ExceededMALLSize = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8871

&mode_lib->ms.support.ExceededMALLSize);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

89

if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8991

mode_lib->ms.support.PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8992

mode_lib->ms.support.DCCMetaBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8996

mode_lib->ms.support.PTEBufferSizeNotExceeded = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8999

mode_lib->ms.support.DCCMetaBufferSizeNotExceeded = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

90

DML_LOG_VERBOSE("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9007

DML_LOG_VERBOSE("DML::%s: PTEBufferSizeNotExceeded = %u\n", __func__, mode_lib->ms.support.PTEBufferSizeNotExceeded);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9008

DML_LOG_VERBOSE("DML::%s: DCCMetaBufferSizeNotExceeded = %u\n", __func__, mode_lib->ms.support.DCCMetaBufferSizeNotExceeded);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

91

if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9193

mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9195

mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9196

mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

92

DML_LOG_VERBOSE("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9201

mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9203

mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen = mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9229

mode_lib->ms.support.InvalidCombinationOfMALLUseForPState = (s->SubViewportMALLPStateMethod != s->PhantomPipeMALLPStateMethod) ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9237

DML_LOG_VERBOSE("DML::%s: InvalidCombinationOfMALLUseForPState = %u\n", __func__, mode_lib->ms.support.InvalidCombinationOfMALLUseForPState);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9244

mode_lib->ms.support.OutstandingRequestsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9245

mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9247

mode_lib->ms.support.avg_urgent_latency_us

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9253

mode_lib->ms.support.avg_non_urgent_latency_us

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9259

mode_lib->ms.support.max_non_urgent_latency_us

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9269

outstanding_latency_us = (mode_lib->soc.max_outstanding_reqs * mode_lib->ms.support.request_size_bytes_luma[k]

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9272

if (outstanding_latency_us < mode_lib->ms.support.avg_urgent_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9273

mode_lib->ms.support.OutstandingRequestsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9276

if (outstanding_latency_us < mode_lib->ms.support.avg_non_urgent_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9277

mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9281

DML_LOG_VERBOSE("DML::%s: avg_urgent_latency_us = %f\n", __func__, mode_lib->ms.support.avg_urgent_latency_us);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9282

DML_LOG_VERBOSE("DML::%s: avg_non_urgent_latency_us = %f\n", __func__, mode_lib->ms.support.avg_non_urgent_latency_us);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9283

DML_LOG_VERBOSE("DML::%s: k=%d, request_size_bytes_luma = %d\n", __func__, k, mode_lib->ms.support.request_size_bytes_luma[k]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9289

outstanding_latency_us = (mode_lib->soc.max_outstanding_reqs * mode_lib->ms.support.request_size_bytes_chroma[k]

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9292

if (outstanding_latency_us < mode_lib->ms.support.avg_urgent_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9293

mode_lib->ms.support.OutstandingRequestsSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9296

if (outstanding_latency_us < mode_lib->ms.support.avg_non_urgent_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9297

mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

93

if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9300

DML_LOG_VERBOSE("DML::%s: k=%d, request_size_bytes_chroma = %d\n", __func__, k, mode_lib->ms.support.request_size_bytes_chroma[k]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9391

mode_lib->ms.support.avg_bandwidth_available_min, // not used

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9392

mode_lib->ms.support.avg_bandwidth_available, // not used

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9393

mode_lib->ms.support.urg_bandwidth_available_min_latency,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9394

mode_lib->ms.support.urg_bandwidth_available, // not used

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9395

mode_lib->ms.support.urg_bandwidth_available_vm_only, // not used

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9396

mode_lib->ms.support.urg_bandwidth_available_pixel_and_vm, // not used

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

94

DML_LOG_VERBOSE("DML: support: DSCCLKRequiredMoreThanSupported = %d\n", support->DSCCLKRequiredMoreThanSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9405

mode_lib->ms.support.avg_bandwidth_available_min,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9406

mode_lib->ms.support.avg_bandwidth_available,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9407

mode_lib->ms.support.urg_bandwidth_available_min,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9408

mode_lib->ms.support.urg_bandwidth_available,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9409

mode_lib->ms.support.urg_bandwidth_available_vm_only,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9410

mode_lib->ms.support.urg_bandwidth_available_pixel_and_vm,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9424

mode_lib->ms.support.avg_bandwidth_required,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9437

mode_lib->ms.support.avg_bandwidth_support_ok[dml2_core_internal_soc_state_sys_idle][m] = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9438

mode_lib->ms.support.avg_bandwidth_support_ok[dml2_core_internal_soc_state_sys_active][m] = (mode_lib->ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][m] <= mode_lib->ms.support.avg_bandwidth_available[dml2_core_internal_soc_state_sys_active][m]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9439

mode_lib->ms.support.avg_bandwidth_support_ok[dml2_core_internal_soc_state_svp_prefetch][m] = (mode_lib->ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][m] <= mode_lib->ms.support.avg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][m]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9442

mode_lib->ms.support.AvgBandwidthSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9443

mode_lib->ms.support.EnoughUrgentLatencyHidingSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9446

mode_lib->ms.support.EnoughUrgentLatencyHidingSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9453

if (!mode_lib->ms.support.avg_bandwidth_support_ok[m][n] && (m == dml2_core_internal_soc_state_sys_active || mode_lib->soc.mall_allocated_for_dcn_mbytes > 0)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9454

mode_lib->ms.support.AvgBandwidthSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9464

mode_lib->ms.support.max_urgent_latency_us = s->mSOCParameters.max_urgent_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9469

/ mode_lib->ms.support.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) >= s->mSOCParameters.max_urgent_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9470

mode_lib->ms.support.ROBSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9472

mode_lib->ms.support.ROBSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9476

mode_lib->ms.support.ROBSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9478

mode_lib->ms.support.ROBSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9499

DML_LOG_VERBOSE("DML::%s: ROBSupport = %u\n", __func__, mode_lib->ms.support.ROBSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

95

if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9504

if (mode_lib->ms.support.ScaleRatioAndTapsSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9505

&& mode_lib->ms.support.SourceFormatPixelAndScanSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9506

&& mode_lib->ms.support.ViewportSizeSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9507

&& !mode_lib->ms.support.LinkRateDoesNotMatchDPVersion

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9508

&& !mode_lib->ms.support.LinkRateForMultistreamNotIndicated

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9509

&& !mode_lib->ms.support.BPPForMultistreamNotIndicated

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9510

&& !mode_lib->ms.support.MultistreamWithHDMIOreDP

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9511

&& !mode_lib->ms.support.ExceededMultistreamSlots

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9512

&& !mode_lib->ms.support.MSOOrODMSplitWithNonDPLink

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9513

&& !mode_lib->ms.support.NotEnoughLanesForMSO

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9514

&& !mode_lib->ms.support.P2IWith420

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9515

&& !mode_lib->ms.support.DSC422NativeNotSupported

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9516

&& mode_lib->ms.support.DSCSlicesODMModeSupported

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9517

&& !mode_lib->ms.support.NotEnoughDSCUnits

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9518

&& !mode_lib->ms.support.NotEnoughDSCSlices

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9519

&& !mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9520

&& !mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9521

&& !mode_lib->ms.support.DSCCLKRequiredMoreThanSupported

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9522

&& mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9523

&& !mode_lib->ms.support.DTBCLKRequiredMoreThanSupported

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9524

&& !mode_lib->ms.support.InvalidCombinationOfMALLUseForPState

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9525

&& mode_lib->ms.support.ROBSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9526

&& mode_lib->ms.support.OutstandingRequestsSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9527

&& mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9528

&& mode_lib->ms.support.DISPCLK_DPPCLK_Support

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9529

&& mode_lib->ms.support.TotalAvailablePipesSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9530

&& mode_lib->ms.support.NumberOfOTGSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9531

&& mode_lib->ms.support.NumberOfHDMIFRLSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9532

&& mode_lib->ms.support.NumberOfDP2p0Support

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9533

&& mode_lib->ms.support.EnoughWritebackUnits

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9534

&& mode_lib->ms.support.WritebackLatencySupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9535

&& mode_lib->ms.support.WritebackScaleRatioAndTapsSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9536

&& mode_lib->ms.support.CursorSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9537

&& mode_lib->ms.support.PitchSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9538

&& !mode_lib->ms.support.ViewportExceedsSurface

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9539

&& mode_lib->ms.support.PrefetchSupported

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9540

&& mode_lib->ms.support.EnoughUrgentLatencyHidingSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9541

&& mode_lib->ms.support.AvgBandwidthSupport

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9542

&& mode_lib->ms.support.DynamicMetadataSupported

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9543

&& mode_lib->ms.support.VRatioInPrefetchSupported

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9544

&& mode_lib->ms.support.PTEBufferSizeNotExceeded

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9545

&& mode_lib->ms.support.DCCMetaBufferSizeNotExceeded

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9546

&& !mode_lib->ms.support.ExceededMALLSize

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9547

&& mode_lib->ms.support.g6_temp_read_support

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9548

&& ((!display_cfg->hostvm_enable && !s->ImmediateFlipRequired) || mode_lib->ms.support.ImmediateFlipSupport)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9550

mode_lib->ms.support.ModeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9553

mode_lib->ms.support.ModeSupport = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9558

DML_LOG_VERBOSE("DML::%s: ModeSupport = %u\n", __func__, mode_lib->ms.support.ModeSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9559

DML_LOG_VERBOSE("DML::%s: ImmediateFlipSupport = %u\n", __func__, mode_lib->ms.support.ImmediateFlipSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9562

mode_lib->ms.support.MPCCombineEnable[k] = mode_lib->ms.MPCCombine[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9563

mode_lib->ms.support.DPPPerSurface[k] = mode_lib->ms.NoOfDPP[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9567

mode_lib->ms.support.ODMMode[k] = mode_lib->ms.ODMMode[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9568

mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9569

mode_lib->ms.support.FECEnabled[k] = mode_lib->ms.RequiresFEC[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9570

mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBpp[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9571

mode_lib->ms.support.OutputType[k] = mode_lib->ms.OutputType[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9572

mode_lib->ms.support.OutputRate[k] = mode_lib->ms.OutputRate[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9575

DML_LOG_VERBOSE("DML::%s: k=%d, ODMMode = %u\n", __func__, k, mode_lib->ms.support.ODMMode[k]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9576

DML_LOG_VERBOSE("DML::%s: k=%d, DSCEnabled = %u\n", __func__, k, mode_lib->ms.support.DSCEnabled[k]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9581

if (!mode_lib->ms.support.ModeSupport)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9582

dml2_print_mode_support_info(&mode_lib->ms.support, true);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9587

return mode_lib->ms.support.ModeSupport;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9598

*in_out_params->out_evaluation_info = in_out_params->mode_lib->ms.support;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

96

DML_LOG_VERBOSE("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support->PixelsPerLinePerDSCUnitSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

97

if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

98

DML_LOG_VERBOSE("DML: support: DTBCLKRequiredMoreThanSupported = %d\n", support->DTBCLKRequiredMoreThanSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

99

if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

378

struct dml2_core_internal_mode_support_info support;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

217

void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

221

if (!fail_only || support->ScaleRatioAndTapsSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

222

DML_LOG_VERBOSE("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

223

if (!fail_only || support->SourceFormatPixelAndScanSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

224

DML_LOG_VERBOSE("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndScanSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

225

if (!fail_only || support->ViewportSizeSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

226

DML_LOG_VERBOSE("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

227

if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

228

DML_LOG_VERBOSE("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPVersion);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

229

if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

230

DML_LOG_VERBOSE("DML: support: LinkRateForMultistreamNotIndicated = %d\n", support->LinkRateForMultistreamNotIndicated);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

231

if (!fail_only || support->BPPForMultistreamNotIndicated == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

232

DML_LOG_VERBOSE("DML: support: BPPForMultistreamNotIndicated = %d\n", support->BPPForMultistreamNotIndicated);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

233

if (!fail_only || support->MultistreamWithHDMIOreDP == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

234

DML_LOG_VERBOSE("DML: support: MultistreamWithHDMIOreDP = %d\n", support->MultistreamWithHDMIOreDP);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

235

if (!fail_only || support->ExceededMultistreamSlots == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

236

DML_LOG_VERBOSE("DML: support: ExceededMultistreamSlots = %d\n", support->ExceededMultistreamSlots);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

237

if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

238

DML_LOG_VERBOSE("DML: support: MSOOrODMSplitWithNonDPLink = %d\n", support->MSOOrODMSplitWithNonDPLink);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

239

if (!fail_only || support->NotEnoughLanesForMSO == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

240

DML_LOG_VERBOSE("DML: support: NotEnoughLanesForMSO = %d\n", support->NotEnoughLanesForMSO);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

241

if (!fail_only || support->P2IWith420 == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

242

DML_LOG_VERBOSE("DML: support: P2IWith420 = %d\n", support->P2IWith420);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

243

if (!fail_only || support->DSC422NativeNotSupported == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

244

DML_LOG_VERBOSE("DML: support: DSC422NativeNotSupported = %d\n", support->DSC422NativeNotSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

245

if (!fail_only || support->DSCSlicesODMModeSupported == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

246

DML_LOG_VERBOSE("DML: support: DSCSlicesODMModeSupported = %d\n", support->DSCSlicesODMModeSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

247

if (!fail_only || support->NotEnoughDSCUnits == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

248

DML_LOG_VERBOSE("DML: support: NotEnoughDSCUnits = %d\n", support->NotEnoughDSCUnits);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

249

if (!fail_only || support->NotEnoughDSCSlices == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

250

DML_LOG_VERBOSE("DML: support: NotEnoughDSCSlices = %d\n", support->NotEnoughDSCSlices);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

251

if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

252

DML_LOG_VERBOSE("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

253

if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

254

DML_LOG_VERBOSE("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

255

if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

256

DML_LOG_VERBOSE("DML: support: DSCCLKRequiredMoreThanSupported = %d\n", support->DSCCLKRequiredMoreThanSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

257

if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

258

DML_LOG_VERBOSE("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support->PixelsPerLinePerDSCUnitSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

259

if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

260

DML_LOG_VERBOSE("DML: support: DTBCLKRequiredMoreThanSupported = %d\n", support->DTBCLKRequiredMoreThanSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

261

if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

262

DML_LOG_VERBOSE("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support->InvalidCombinationOfMALLUseForPState);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

263

if (!fail_only || support->ROBSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

264

DML_LOG_VERBOSE("DML: support: ROBSupport = %d\n", support->ROBSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

265

if (!fail_only || support->OutstandingRequestsSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

266

DML_LOG_VERBOSE("DML: support: OutstandingRequestsSupport = %d\n", support->OutstandingRequestsSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

267

if (!fail_only || support->OutstandingRequestsUrgencyAvoidance == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

268

DML_LOG_VERBOSE("DML: support: OutstandingRequestsUrgencyAvoidance = %d\n", support->OutstandingRequestsUrgencyAvoidance);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

269

if (!fail_only || support->DISPCLK_DPPCLK_Support == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

270

DML_LOG_VERBOSE("DML: support: DISPCLK_DPPCLK_Support = %d\n", support->DISPCLK_DPPCLK_Support);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

271

if (!fail_only || support->TotalAvailablePipesSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

272

DML_LOG_VERBOSE("DML: support: TotalAvailablePipesSupport = %d\n", support->TotalAvailablePipesSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

273

if (!fail_only || support->NumberOfOTGSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

274

DML_LOG_VERBOSE("DML: support: NumberOfOTGSupport = %d\n", support->NumberOfOTGSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

275

if (!fail_only || support->NumberOfHDMIFRLSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

276

DML_LOG_VERBOSE("DML: support: NumberOfHDMIFRLSupport = %d\n", support->NumberOfHDMIFRLSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

277

if (!fail_only || support->NumberOfDP2p0Support == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

278

DML_LOG_VERBOSE("DML: support: NumberOfDP2p0Support = %d\n", support->NumberOfDP2p0Support);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

279

if (!fail_only || support->EnoughWritebackUnits == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

280

DML_LOG_VERBOSE("DML: support: EnoughWritebackUnits = %d\n", support->EnoughWritebackUnits);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

281

if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

282

DML_LOG_VERBOSE("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support->WritebackScaleRatioAndTapsSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

283

if (!fail_only || support->WritebackLatencySupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

284

DML_LOG_VERBOSE("DML: support: WritebackLatencySupport = %d\n", support->WritebackLatencySupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

285

if (!fail_only || support->CursorSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

286

DML_LOG_VERBOSE("DML: support: CursorSupport = %d\n", support->CursorSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

287

if (!fail_only || support->PitchSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

288

DML_LOG_VERBOSE("DML: support: PitchSupport = %d\n", support->PitchSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

289

if (!fail_only || support->ViewportExceedsSurface == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

290

DML_LOG_VERBOSE("DML: support: ViewportExceedsSurface = %d\n", support->ViewportExceedsSurface);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

291

if (!fail_only || support->PrefetchSupported == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

292

DML_LOG_VERBOSE("DML: support: PrefetchSupported = %d\n", support->PrefetchSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

293

if (!fail_only || support->EnoughUrgentLatencyHidingSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

294

DML_LOG_VERBOSE("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support->EnoughUrgentLatencyHidingSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

295

if (!fail_only || support->AvgBandwidthSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

296

DML_LOG_VERBOSE("DML: support: AvgBandwidthSupport = %d\n", support->AvgBandwidthSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

297

if (!fail_only || support->DynamicMetadataSupported == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

298

DML_LOG_VERBOSE("DML: support: DynamicMetadataSupported = %d\n", support->DynamicMetadataSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

299

if (!fail_only || support->VRatioInPrefetchSupported == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

300

DML_LOG_VERBOSE("DML: support: VRatioInPrefetchSupported = %d\n", support->VRatioInPrefetchSupported);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

301

if (!fail_only || support->PTEBufferSizeNotExceeded == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

302

DML_LOG_VERBOSE("DML: support: PTEBufferSizeNotExceeded = %d\n", support->PTEBufferSizeNotExceeded);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

303

if (!fail_only || support->DCCMetaBufferSizeNotExceeded == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

304

DML_LOG_VERBOSE("DML: support: DCCMetaBufferSizeNotExceeded = %d\n", support->DCCMetaBufferSizeNotExceeded);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

305

if (!fail_only || support->ExceededMALLSize == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

306

DML_LOG_VERBOSE("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

307

if (!fail_only || support->g6_temp_read_support == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

308

DML_LOG_VERBOSE("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

309

if (!fail_only || support->ImmediateFlipSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

310

DML_LOG_VERBOSE("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

311

if (!fail_only || support->LinkCapacitySupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

312

DML_LOG_VERBOSE("DML: support: LinkCapacitySupport = %d\n", support->LinkCapacitySupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

314

if (!fail_only || support->ModeSupport == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

315

DML_LOG_VERBOSE("DML: support: ModeSupport = %d\n", support->ModeSupport);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h

16

void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

288

if (in_ctx->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0] == dml_fclock_change_unsupported)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

656

*fclk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

657

*dram_clk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.DRAMClockChangeSupport[0];

sys/dev/pci/drm/amd/display/modules/inc/mod_info_packet.h

61

bool support;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

575

info_packet->sb[4] = (param->increase.support << 6 | param->decrease.support << 7);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

344

#define PP_CG_MSG_ID(group, block, support, state) \

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

346

(support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)