sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1007

spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_subsampled);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1011

spl_scratch->scl_data.taps.h_taps = 6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1012

spl_scratch->scl_data.taps.v_taps = 6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1013

spl_scratch->scl_data.taps.h_taps_c = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1014

spl_scratch->scl_data.taps.v_taps_c = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1016

spl_scratch->scl_data.taps.h_taps = 6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1017

spl_scratch->scl_data.taps.v_taps = 6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1018

spl_scratch->scl_data.taps.h_taps_c = 6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1019

spl_scratch->scl_data.taps.v_taps_c = 6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1024

min_taps_y = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1025

min_taps_c = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1033

spl_in->callbacks.spl_calc_lb_num_partitions(spl_in->basic_out.alpha_en, &spl_scratch->scl_data,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1036

if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 2)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1037

if ((spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) - 2) > num_part_y)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1040

max_taps_y = num_part_y - (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) - 2);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1044

if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 2)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1045

if ((spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) - 2) > num_part_c)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1048

max_taps_c = num_part_c - (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) - 2);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1057

if (spl_scratch->scl_data.taps.v_taps > max_taps_y)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1058

spl_scratch->scl_data.taps.v_taps = max_taps_y;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1060

if (spl_scratch->scl_data.taps.v_taps_c > max_taps_c)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1061

spl_scratch->scl_data.taps.v_taps_c = max_taps_c;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1078

if (spl_scratch->scl_data.taps.v_taps == 5)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1079

spl_scratch->scl_data.taps.v_taps = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1081

if (spl_scratch->scl_data.taps.v_taps_c == 5)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1082

spl_scratch->scl_data.taps.v_taps_c = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1084

if (spl_scratch->scl_data.taps.h_taps == 5)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1085

spl_scratch->scl_data.taps.h_taps = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1087

if (spl_scratch->scl_data.taps.h_taps_c == 5)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1088

spl_scratch->scl_data.taps.h_taps_c = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1091

if (spl_scratch->scl_data.taps.h_taps <= 4) {

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1094

} else if (spl_scratch->scl_data.taps.v_taps <= 3) {

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1101

SPL_ASSERT((spl_scratch->scl_data.taps.v_taps > 1) &&

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1102

(spl_scratch->scl_data.taps.v_taps_c > 1));

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1104

if (spl_scratch->scl_data.taps.h_taps <= 3) {

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1107

} else if (spl_scratch->scl_data.taps.v_taps < 3) {

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1114

SPL_ASSERT(spl_scratch->scl_data.taps.v_taps > 1);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1128

*enable_isharp = spl_get_isharp_en(spl_in, spl_scratch);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1130

if ((IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz)) &&

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1131

(IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert))) {

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1132

spl_scratch->scl_data.taps.h_taps = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1133

spl_scratch->scl_data.taps.v_taps = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1134

if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c) && !is_subsampled)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1135

spl_scratch->scl_data.taps.h_taps_c = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1137

if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c) && !is_subsampled)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1138

spl_scratch->scl_data.taps.v_taps_c = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1144

(IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz)))

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1145

spl_scratch->scl_data.taps.h_taps = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1148

(IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert)))

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1149

spl_scratch->scl_data.taps.v_taps = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1152

(IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c)))

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1153

spl_scratch->scl_data.taps.h_taps_c = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1156

(IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c)))

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1157

spl_scratch->scl_data.taps.v_taps_c = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1224

static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_scratch *spl_scratch,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1229

const struct spl_scaler_data *data = &spl_scratch->scl_data;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1236

dscl_prog_data->recout = spl_scratch->scl_data.recout;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1238

dscl_prog_data->mpc_size.width = spl_scratch->scl_data.h_active;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1239

dscl_prog_data->mpc_size.height = spl_scratch->scl_data.v_active;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1254

dscl_prog_data->viewport = spl_scratch->scl_data.viewport;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1256

dscl_prog_data->viewport_c = spl_scratch->scl_data.viewport_c;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1300

static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *spl_out, bool enable_easf_v,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1314

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1317

spl_get_3tap_dntilt_uptilt_offset(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1318

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1321

spl_get_3tap_uptilt_maxval(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1322

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1325

spl_get_3tap_dntilt_slope(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1326

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1329

spl_get_3tap_uptilt1_slope(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1330

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1333

spl_get_3tap_uptilt2_slope(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1334

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1337

spl_get_3tap_uptilt2_offset(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1338

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1341

spl_get_reducer_gain4(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1342

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1345

spl_get_reducer_gain6(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1346

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1349

spl_get_gainRing4(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1350

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1353

spl_get_gainRing6(spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1354

spl_scratch->scl_data.recip_ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1480

spl_scratch->scl_data.recip_ratios.horz);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1483

spl_get_reducer_gain4(spl_scratch->scl_data.taps.h_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1484

spl_scratch->scl_data.recip_ratios.horz);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1487

spl_get_reducer_gain6(spl_scratch->scl_data.taps.h_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1488

spl_scratch->scl_data.recip_ratios.horz);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1491

spl_get_gainRing4(spl_scratch->scl_data.taps.h_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1492

spl_scratch->scl_data.recip_ratios.horz);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1495

spl_get_gainRing6(spl_scratch->scl_data.taps.h_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1496

spl_scratch->scl_data.recip_ratios.horz);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1802

static bool spl_calculate_number_of_taps(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1807

memset(spl_scratch, 0, sizeof(struct spl_scratch));

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1808

spl_scratch->scl_data.h_active = spl_in->h_active;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1809

spl_scratch->scl_data.v_active = spl_in->v_active;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1814

spl_calculate_recout(spl_in, spl_scratch, spl_out);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1816

spl_calculate_scaling_ratios(spl_in, spl_scratch, spl_out);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1818

spl_opp_adjust_rect(&spl_scratch->scl_data.recout, &spl_in->basic_in.opp_recout_adjust);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1820

spl_calculate_viewport_size(spl_in, spl_scratch);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1824

spl_scratch, &spl_in->scaling_quality, enable_easf_v,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1837

struct spl_scratch spl_scratch;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1841

const struct spl_scaler_data *data = &spl_scratch.scl_data;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1843

res = spl_calculate_number_of_taps(spl_in, &spl_scratch, spl_out,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1851

spl_calculate_inits_and_viewports(spl_in, &spl_scratch);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1853

spl_handle_3d_recout(spl_in, &spl_scratch.scl_data.recout);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1855

spl_clamp_viewport(&spl_scratch.scl_data.viewport, spl_in->min_viewport_size);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1858

spl_set_dscl_prog_data(spl_in, &spl_scratch, spl_out, enable_easf_v, enable_easf_h, enable_isharp);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1876

spl_set_easf_data(&spl_scratch, spl_out, enable_easf_v, enable_easf_h, spl_in->lls_pref,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1880

vratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1881

hratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.horz);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1883

isharp_scale_ratio = spl_scratch.scl_data.recip_ratios.vert;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1885

isharp_scale_ratio = spl_scratch.scl_data.recip_ratios.horz;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1901

struct spl_scratch spl_scratch;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1903

const struct spl_scaler_data *data = &spl_scratch.scl_data;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1905

res = spl_calculate_number_of_taps(spl_in, &spl_scratch, spl_out,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

273

static void spl_calculate_recout(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

416

spl_scratch->scl_data.recout = shift_rec(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

419

spl_scratch->scl_data.recout.height -=

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

421

spl_scratch->scl_data.recout.height -=

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

425

memset(&spl_scratch->scl_data.recout, 0,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

431

struct spl_scratch *spl_scratch,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

445

spl_scratch->scl_data.ratios.horz = spl_fixpt_from_fraction(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

448

spl_scratch->scl_data.ratios.vert = spl_fixpt_from_fraction(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

453

spl_scratch->scl_data.ratios.horz.value *= 2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

455

spl_scratch->scl_data.ratios.vert.value *= 2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

457

spl_scratch->scl_data.ratios.vert.value = spl_div64_s64(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

458

spl_scratch->scl_data.ratios.vert.value * in_h, out_h);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

459

spl_scratch->scl_data.ratios.horz.value = spl_div64_s64(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

460

spl_scratch->scl_data.ratios.horz.value * in_w, out_w);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

462

spl_scratch->scl_data.ratios.horz_c = spl_scratch->scl_data.ratios.horz;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

463

spl_scratch->scl_data.ratios.vert_c = spl_scratch->scl_data.ratios.vert;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

466

spl_scratch->scl_data.ratios.horz_c.value /= 2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

467

spl_scratch->scl_data.ratios.vert_c.value /= 2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

469

spl_scratch->scl_data.ratios.horz = spl_fixpt_truncate(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

470

spl_scratch->scl_data.ratios.horz, 19);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

471

spl_scratch->scl_data.ratios.vert = spl_fixpt_truncate(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

472

spl_scratch->scl_data.ratios.vert, 19);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

473

spl_scratch->scl_data.ratios.horz_c = spl_fixpt_truncate(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

474

spl_scratch->scl_data.ratios.horz_c, 19);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

475

spl_scratch->scl_data.ratios.vert_c = spl_fixpt_truncate(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

476

spl_scratch->scl_data.ratios.vert_c, 19);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

483

spl_scratch->scl_data.recip_ratios.horz = spl_fixpt_recip(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

484

spl_scratch->scl_data.ratios.horz);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

485

spl_scratch->scl_data.recip_ratios.vert = spl_fixpt_recip(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

486

spl_scratch->scl_data.ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

487

spl_scratch->scl_data.recip_ratios.horz_c = spl_fixpt_recip(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

488

spl_scratch->scl_data.ratios.horz_c);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

489

spl_scratch->scl_data.recip_ratios.vert_c = spl_fixpt_recip(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

490

spl_scratch->scl_data.ratios.vert_c);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

494

static void spl_calculate_viewport_size(struct spl_in *spl_in, struct spl_scratch *spl_scratch)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

496

spl_scratch->scl_data.viewport.width = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.horz,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

497

spl_scratch->scl_data.recout.width));

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

498

spl_scratch->scl_data.viewport.height = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.vert,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

499

spl_scratch->scl_data.recout.height));

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

500

spl_scratch->scl_data.viewport_c.width = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.horz_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

501

spl_scratch->scl_data.recout.width));

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

502

spl_scratch->scl_data.viewport_c.height = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.vert_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

503

spl_scratch->scl_data.recout.height));

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

506

spl_swap(spl_scratch->scl_data.viewport.width, spl_scratch->scl_data.viewport.height);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

507

spl_swap(spl_scratch->scl_data.viewport_c.width, spl_scratch->scl_data.viewport_c.height);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

604

struct spl_scratch *spl_scratch)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

618

&spl_scratch->scl_data.recout, odm_slice.x, odm_slice.y);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

673

spl_scratch->scl_data.recout.width,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

675

spl_scratch->scl_data.taps.h_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

676

spl_scratch->scl_data.ratios.horz,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

678

&spl_scratch->scl_data.inits.h,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

679

&spl_scratch->scl_data.viewport.x,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

680

&spl_scratch->scl_data.viewport.width);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

684

spl_scratch->scl_data.recout.width,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

686

spl_scratch->scl_data.taps.h_taps_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

687

spl_scratch->scl_data.ratios.horz_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

689

&spl_scratch->scl_data.inits.h_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

690

&spl_scratch->scl_data.viewport_c.x,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

691

&spl_scratch->scl_data.viewport_c.width);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

695

spl_scratch->scl_data.recout.height,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

697

spl_scratch->scl_data.taps.v_taps,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

698

spl_scratch->scl_data.ratios.vert,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

700

&spl_scratch->scl_data.inits.v,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

701

&spl_scratch->scl_data.viewport.y,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

702

&spl_scratch->scl_data.viewport.height);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

706

spl_scratch->scl_data.recout.height,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

708

spl_scratch->scl_data.taps.v_taps_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

709

spl_scratch->scl_data.ratios.vert_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

711

&spl_scratch->scl_data.inits.v_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

712

&spl_scratch->scl_data.viewport_c.y,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

713

&spl_scratch->scl_data.viewport_c.height);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

715

spl_swap(spl_scratch->scl_data.viewport.x, spl_scratch->scl_data.viewport.y);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

716

spl_swap(spl_scratch->scl_data.viewport.width, spl_scratch->scl_data.viewport.height);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

717

spl_swap(spl_scratch->scl_data.viewport_c.x, spl_scratch->scl_data.viewport_c.y);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

718

spl_swap(spl_scratch->scl_data.viewport_c.width, spl_scratch->scl_data.viewport_c.height);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

720

spl_scratch->scl_data.viewport.x += src.x;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

721

spl_scratch->scl_data.viewport.y += src.y;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

723

spl_scratch->scl_data.viewport_c.x += src.x / vpc_div;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

724

spl_scratch->scl_data.viewport_c.y += src.y / vpc_div;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

801

static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

810

vratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

811

hratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

844

struct spl_scratch *spl_scratch)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

849

struct spl_taps taps = spl_scratch->scl_data.taps;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

856

vratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

857

hratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

892

struct spl_scratch *spl_scratch,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

899

if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz) > 1)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

900

spl_scratch->scl_data.taps.h_taps = spl_min(2 * spl_fixpt_ceil(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

901

spl_scratch->scl_data.ratios.horz), 8);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

903

spl_scratch->scl_data.taps.h_taps = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

905

spl_scratch->scl_data.taps.h_taps = in_taps->h_taps;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

908

if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 1)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

909

spl_scratch->scl_data.taps.v_taps = spl_min(2 * spl_fixpt_ceil(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

910

spl_scratch->scl_data.ratios.vert), 8);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

912

spl_scratch->scl_data.taps.v_taps = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

914

spl_scratch->scl_data.taps.v_taps = in_taps->v_taps;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

917

if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 1)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

918

spl_scratch->scl_data.taps.v_taps_c = spl_min(2 * spl_fixpt_ceil(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

919

spl_scratch->scl_data.ratios.vert_c), 8);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

921

spl_scratch->scl_data.taps.v_taps_c = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

923

spl_scratch->scl_data.taps.v_taps_c = in_taps->v_taps_c;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

926

if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz_c) > 1)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

927

spl_scratch->scl_data.taps.h_taps_c = spl_min(2 * spl_fixpt_ceil(

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

928

spl_scratch->scl_data.ratios.horz_c), 8);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

930

spl_scratch->scl_data.taps.h_taps_c = 4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

933

spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

935

spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

941

check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.horz,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

944

check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.vert,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

947

check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.horz_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

950

check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.vert_c,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

955

if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz))

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

956

spl_scratch->scl_data.taps.h_taps = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

957

if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert))

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

958

spl_scratch->scl_data.taps.v_taps = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

959

if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c) && !is_subsampled)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

960

spl_scratch->scl_data.taps.h_taps_c = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

961

if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c) && !is_subsampled)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

962

spl_scratch->scl_data.taps.v_taps_c = 1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

968

int max_downscale_src_width, struct spl_in *spl_in, struct spl_scratch *spl_scratch,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

979

if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active &&

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

981

spl_scratch->scl_data.viewport.width > max_downscale_src_width) {

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

982

spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_subsampled);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

991

spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_subsampled);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

999

skip_easf = enable_easf(spl_in, spl_scratch);