Symbol: spl_in
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1479
struct spl_in *spl_in = &pipe_ctx->plane_res.spl_in;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1490
translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1493
&spl_in->debug.visual_confirm_base_offset,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1494
&spl_in->debug.visual_confirm_dpp_offset);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1498
res = spl_calculate_scaler_params(spl_in, spl_out);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
100
spl_in->basic_out.view_format = (enum spl_view_3d)stream->view_format;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
102
populate_splrect_from_rect(&spl_in->basic_in.clip_rect, &plane_state->clip_rect);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
104
populate_splrect_from_rect(&spl_in->basic_out.src_rect, &stream->src);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
106
populate_splrect_from_rect(&spl_in->basic_out.dst_rect, &stream->dst);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
108
spl_in->basic_in.rotation = (enum spl_rotation_angle)plane_state->rotation;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
110
populate_splrect_from_rect(&spl_in->basic_in.src_rect, &plane_state->src_rect);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
112
populate_splrect_from_rect(&spl_in->basic_in.dst_rect, &plane_state->dst_rect);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
114
spl_in->basic_in.horizontal_mirror = plane_state->horizontal_mirror;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
117
spl_in->basic_in.num_h_slices_recout_width_align.use_recout_width_aligned = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
118
spl_in->basic_in.num_h_slices_recout_width_align.num_slices_recout_width.mpc_num_h_slices =
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
122
spl_in->basic_in.mpc_h_slice_index = 0;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
124
spl_in->basic_in.mpc_h_slice_index = resource_get_mpc_slice_index(pipe_ctx);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
126
populate_splrect_from_rect(&spl_in->basic_out.odm_slice_rect, &odm_slice_src);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
127
spl_in->basic_out.odm_combine_factor = 0;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
128
spl_in->odm_slice_index = resource_get_odm_slice_index(pipe_ctx);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
130
spl_in->basic_out.output_size.width =
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
133
spl_in->basic_out.output_size.height =
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
135
spl_in->basic_out.max_downscale_src_width =
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
137
spl_in->basic_out.always_scale = pipe_ctx->stream->ctx->dc->debug.always_scale;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
139
spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
140
spl_in->basic_out.use_two_pixels_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
142
populate_spltaps_from_taps(&spl_in->scaling_quality, &plane_state->scaling_quality);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
144
spl_in->prefer_easf = pipe_ctx->stream->ctx->dc->config.prefer_easf;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
145
spl_in->disable_easf = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
147
spl_in->prefer_easf = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
149
spl_in->disable_easf = true;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
154
spl_in->adaptive_sharpness.enable = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
156
spl_in->adaptive_sharpness.enable = true;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
157
spl_in->adaptive_sharpness.sharpness_level = 0;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
160
spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_min = plane_state->sharpness_range.sdr_rgb_min;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
161
spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_max = plane_state->sharpness_range.sdr_rgb_max;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
162
spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_mid = plane_state->sharpness_range.sdr_rgb_mid;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
163
spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_min = plane_state->sharpness_range.sdr_yuv_min;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
164
spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_max = plane_state->sharpness_range.sdr_yuv_max;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
165
spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_mid = plane_state->sharpness_range.sdr_yuv_mid;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
166
spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_min = plane_state->sharpness_range.hdr_rgb_min;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
167
spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_max = plane_state->sharpness_range.hdr_rgb_max;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
168
spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_mid = plane_state->sharpness_range.hdr_rgb_mid;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
173
spl_in->adaptive_sharpness.enable = true;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
174
spl_in->adaptive_sharpness.sharpness_level = force_sharpness_level;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
176
spl_in->adaptive_sharpness.enable = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
177
spl_in->adaptive_sharpness.sharpness_level = 0;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
179
spl_in->adaptive_sharpness.enable = true;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
180
spl_in->adaptive_sharpness.sharpness_level = plane_state->sharpness_level;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
185
spl_in->lls_pref = pipe_ctx->stream->ctx->dc->debug.force_lls;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
187
spl_in->lls_pref = plane_state->linear_light_scaling;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
190
spl_in->basic_in.cositing = pipe_ctx->stream->ctx->dc->debug.force_cositing - 1;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
192
spl_in->basic_in.cositing = plane_state->cositing;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
194
spl_in->basic_in.tf_type = (enum spl_transfer_func_type) plane_state->in_transfer_func.type;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
195
spl_in->basic_in.tf_predefined_type = (enum spl_transfer_func_predefined) plane_state->in_transfer_func.tf;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
197
spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
198
spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
200
spl_in->sharpen_policy = (enum sharpen_policy)plane_state->adaptive_sharpness_policy;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
201
spl_in->debug.scale_to_sharpness_policy =
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
207
spl_in->is_fullscreen = pipe_ctx->stream->sharpening_required;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
208
spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
209
spl_in->sdr_white_level_nits = plane_state->sdr_white_level_nits;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
76
void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in)
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
86
spl_in->callbacks = dcn2_spl_callbacks;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
89
spl_in->callbacks = dcn32_spl_callbacks;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
92
spl_in->callbacks = dcn401_spl_callbacks;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
95
spl_in->callbacks = dcn2_spl_callbacks;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
98
populate_splformat_from_format(&spl_in->basic_in.format, pipe_ctx->plane_res.scl_data.format);
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.h
15
void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in);
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
374
struct spl_in spl_in;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1010
if (spl_is_video_format(spl_in->basic_in.format)) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1028
if (spl_is_yuv420(spl_in->basic_in.format))
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1033
spl_in->callbacks.spl_calc_lb_num_partitions(spl_in->basic_out.alpha_en, &spl_scratch->scl_data,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1090
if (spl_is_video_format(spl_in->basic_in.format)) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1128
*enable_isharp = spl_get_isharp_en(spl_in, spl_scratch);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1129
if (!*enable_isharp && !spl_in->basic_out.always_scale) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1224
static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_scratch *spl_scratch,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1242
dscl_prog_data->dscl_mode = spl_get_dscl_mode(spl_in, data, enable_isharp,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1246
spl_set_black_color_data(spl_in->basic_in.format, scl_black_color);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
158
const struct spl_rect *stream_src = &spl_in->basic_out.src_rect;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
159
const struct spl_rect *stream_dst = &spl_in->basic_out.dst_rect;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1802
static bool spl_calculate_number_of_taps(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1808
spl_scratch->scl_data.h_active = spl_in->h_active;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1809
spl_scratch->scl_data.v_active = spl_in->v_active;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1814
spl_calculate_recout(spl_in, spl_scratch, spl_out);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1816
spl_calculate_scaling_ratios(spl_in, spl_scratch, spl_out);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1818
spl_opp_adjust_rect(&spl_scratch->scl_data.recout, &spl_in->basic_in.opp_recout_adjust);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1820
spl_calculate_viewport_size(spl_in, spl_scratch);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1823
spl_in->basic_out.max_downscale_src_width, spl_in,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1824
spl_scratch, &spl_in->scaling_quality, enable_easf_v,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1830
bool SPL_NAMESPACE(spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out))
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1843
res = spl_calculate_number_of_taps(spl_in, &spl_scratch, spl_out,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1851
spl_calculate_inits_and_viewports(spl_in, &spl_scratch);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1853
spl_handle_3d_recout(spl_in, &spl_scratch.scl_data.recout);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1855
spl_clamp_viewport(&spl_scratch.scl_data.viewport, spl_in->min_viewport_size);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1858
spl_set_dscl_prog_data(spl_in, &spl_scratch, spl_out, enable_easf_v, enable_easf_h, enable_isharp);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
186
struct spl_in *spl_in,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1863
if (spl_in->lls_pref == LLS_PREF_YES) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1864
if (spl_in->is_hdr_on)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1869
if (spl_in->is_hdr_on)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1876
spl_set_easf_data(&spl_scratch, spl_out, enable_easf_v, enable_easf_h, spl_in->lls_pref,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1877
spl_in->basic_in.format, setup, spl_in->sdr_white_level_nits);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1887
spl_set_isharp_data(spl_out->dscl_prog_data, spl_in->adaptive_sharpness, enable_isharp,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1888
spl_in->lls_pref, spl_in->basic_in.format, data, isharp_scale_ratio, setup,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1889
spl_in->debug.scale_to_sharpness_policy);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1895
bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_out *spl_out))
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
190
spl_in->basic_in.num_h_slices_recout_width_align.use_recout_width_aligned;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1905
res = spl_calculate_number_of_taps(spl_in, &spl_scratch, spl_out,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
192
spl_in->basic_in.num_h_slices_recout_width_align.num_slices_recout_width.mpc_num_h_slices;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
194
spl_in->basic_in.num_h_slices_recout_width_align.num_slices_recout_width.mpc_recout_width_align;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
195
int mpc_slice_idx = spl_in->basic_in.mpc_h_slice_index;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
199
if (spl_in->basic_in.custom_width != 0) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
200
mpc_rec.width = spl_in->basic_in.custom_width;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
201
mpc_rec.x = spl_in->basic_in.custom_x;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
221
spl_in->basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE ||
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
227
if (mpc_slice_idx > epimo && spl_in->basic_in.custom_width == 0) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
232
if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
239
static struct spl_rect calculate_odm_slice_in_timing_active(struct spl_in *spl_in)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
241
int odm_slice_count = spl_in->basic_out.odm_combine_factor;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
242
int odm_slice_idx = spl_in->odm_slice_index;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
244
int h_active = spl_in->basic_out.output_size.width;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
245
int v_active = spl_in->basic_out.output_size.height;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
249
if (spl_in->basic_out.odm_combine_factor > 0) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
255
if (spl_in->basic_out.use_two_pixels_per_container && (odm_slice_width % 2))
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
270
return spl_in->basic_out.odm_slice_rect;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
273
static void spl_calculate_recout(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
401
plane_clip = calculate_plane_rec_in_timing_active(spl_in,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
402
&spl_in->basic_in.clip_rect);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
405
&spl_in->basic_out.dst_rect);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
407
spl_in, &plane_clip);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
408
odm_slice = calculate_odm_slice_in_timing_active(spl_in);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
420
spl_in->debug.visual_confirm_base_offset;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
422
spl_in->debug.visual_confirm_dpp_offset;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
430
static void spl_calculate_scaling_ratios(struct spl_in *spl_in,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
434
const int in_w = spl_in->basic_out.src_rect.width;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
435
const int in_h = spl_in->basic_out.src_rect.height;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
436
const int out_w = spl_in->basic_out.dst_rect.width;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
437
const int out_h = spl_in->basic_out.dst_rect.height;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
438
struct spl_rect surf_src = spl_in->basic_in.src_rect;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
441
if (spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_90 ||
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
442
spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_270)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
447
spl_in->basic_in.dst_rect.width);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
450
spl_in->basic_in.dst_rect.height);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
452
if (spl_in->basic_out.view_format == SPL_VIEW_3D_SIDE_BY_SIDE)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
454
else if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
465
if (spl_is_yuv420(spl_in->basic_in.format)) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
494
static void spl_calculate_viewport_size(struct spl_in *spl_in, struct spl_scratch *spl_scratch)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
504
if (spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_90 ||
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
505
spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_270) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
603
static void spl_calculate_inits_and_viewports(struct spl_in *spl_in,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
606
struct spl_rect src = spl_in->basic_in.src_rect;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
611
struct spl_rect odm_slice = calculate_odm_slice_in_timing_active(spl_in);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
612
int vpc_div = spl_is_subsampled_format(spl_in->basic_in.format) ? 2 : 1;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
620
spl_in, &spl_in->basic_in.dst_rect);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
634
spl_in->basic_in.rotation,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
635
spl_in->basic_in.horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
640
if (spl_is_subsampled_format(spl_in->basic_in.format)) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
647
switch (spl_in->basic_in.cositing) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
727
static void spl_handle_3d_recout(struct spl_in *spl_in, struct spl_rect *recout)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
734
if (spl_in->basic_in.mpc_h_slice_index) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
735
SPL_ASSERT(spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_0 ||
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
736
(spl_in->basic_out.view_format != SPL_VIEW_3D_TOP_AND_BOTTOM &&
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
737
spl_in->basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE));
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
738
if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
740
else if (spl_in->basic_out.view_format == SPL_VIEW_3D_SIDE_BY_SIDE)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
756
static enum scl_mode spl_get_dscl_mode(const struct spl_in *spl_in,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
761
enum spl_pixel_format pixel_format = spl_in->basic_in.format;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
768
&& !spl_in->basic_out.always_scale
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
784
if (data->ratios.horz.value == one && data->ratios.vert.value == one && !spl_in->basic_out.always_scale)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
801
static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
807
if (spl_in->disable_easf)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
824
if (spl_in->lls_pref == LLS_PREF_DONT_CARE)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
825
spl_choose_lls_policy(spl_in->basic_in.format,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
826
&spl_in->lls_pref);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
829
if (spl_in->lls_pref != LLS_PREF_YES && !spl_in->prefer_easf)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
836
static bool spl_is_video_fullscreen(struct spl_in *spl_in)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
838
if (spl_is_video_format(spl_in->basic_in.format) && spl_in->is_fullscreen)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
843
static bool spl_get_isharp_en(struct spl_in *spl_in,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
850
bool fullscreen = spl_is_video_fullscreen(spl_in);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
853
if (spl_in->adaptive_sharpness.enable == false)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
869
if (!spl_is_video_format(spl_in->basic_in.format) &&
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
870
(spl_in->sharpen_policy == SHARPEN_YUV))
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
872
else if ((spl_is_video_format(spl_in->basic_in.format) && !fullscreen) &&
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
873
(spl_in->sharpen_policy == SHARPEN_RGB_FULLSCREEN_YUV))
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
875
else if (!spl_in->is_fullscreen &&
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
876
spl_in->sharpen_policy == SHARPEN_FULLSCREEN_ALL)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
94
struct spl_in *spl_in,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
968
int max_downscale_src_width, struct spl_in *spl_in, struct spl_scratch *spl_scratch,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
977
bool is_subsampled = spl_is_subsampled_format(spl_in->basic_in.format);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
990
if (spl_in->scaling_quality.integer_scaling) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
999
skip_easf = enable_easf(spl_in, spl_scratch);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.h
23
bool SPL_NAMESPACE(spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out));
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.h
25
bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_out *spl_out));