status_page
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
return (i915_ggtt_offset(engine->status_page.vma) +
return READ_ONCE(engine->status_page.addr[reg]);
drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
WRITE_ONCE(engine->status_page.addr[reg], value);
drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
vma = fetch_and_zero(&engine->status_page.vma);
INIT_LIST_HEAD(&engine->status_page.timelines);
engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
engine->status_page.vma = vma;
struct i915_vma *hwsp = engine->status_page.vma;
&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
hexdump(m, engine->status_page.addr, PAGE_SIZE);
GEM_BUG_ON(ce->timeline->hwsp_ggtt != engine->status_page.vma);
struct intel_hw_status_page status_page;
engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;
list_for_each_entry(tl, &engine->status_page.timelines, engine_link)
memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);
drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
i915_ggtt_offset(engine->status_page.vma));
(u64 *)&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
&engine->status_page.addr[INTEL_HWS_CSB_WRITE_INDEX(i915)];
set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));
GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
list_for_each_entry(tl, &engine->status_page.timelines, engine_link)
memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);
drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
struct drm_i915_gem_object *obj = engine->status_page.vma->obj;
set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));
struct i915_vma *hwsp = engine->status_page.vma;
list_add_tail(&tl->engine_link, &engine->status_page.timelines);
engine->base.status_page.addr = (void *)(engine + 1);
engine->status_page.vma = ce->timeline->hwsp_ggtt;
i915_ggtt_offset(ce->engine->status_page.vma) +
slot = memset32(engine->status_page.addr + 1000, 0, 4);
*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
i915_ggtt_offset(ce->engine->status_page.vma) +
u32 *slot = memset32(engine->status_page.addr + 1000, 0, 4);
i915_ggtt_offset(ce->engine->status_page.vma) +
u32 *slot = memset32(arg->engine->status_page.addr + 1000, 0, 4);
i915_ggtt_offset(ce->engine->status_page.vma) +
list_for_each_entry(tl, &engine->status_page.timelines, engine_link)
memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);
drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
i915_ggtt_offset(engine->status_page.vma));
add_vma_coredump(ee, engine->gt, engine->status_page.vma,
store = memset32(rq->engine->status_page.addr + 512, 0, 32);
*cs++ = i915_ggtt_offset(rq->engine->status_page.vma) +
return memset32(ce->engine->status_page.addr + 1000, 0, 21);
return (i915_ggtt_offset(ce->engine->status_page.vma) +
i915_ggtt_offset(engine->status_page.vma) +