sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

260

int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1849

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2161

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2376

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2378

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2856

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2861

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1549

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1863

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2128

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2130

ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1097

ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);