smu_dpm_clks
struct smu_dpm_clks *smu_dpm_clks)
struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
smu_dpm_clks->mc_address.high_part);
smu_dpm_clks->mc_address.low_part);
struct smu_dpm_clks smu_dpm_clks = { 0 };
smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(
&smu_dpm_clks.mc_address.quad_part);
if (smu_dpm_clks.dpm_clks == NULL) {
smu_dpm_clks.dpm_clks = &dummy_clocks;
smu_dpm_clks.mc_address.quad_part = 0;
ASSERT(smu_dpm_clks.dpm_clks);
vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
smu_dpm_clks.dpm_clks);
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
smu_dpm_clks.dpm_clks);
struct dcn31_smu_dpm_clks *smu_dpm_clks)
DpmClocks_t *table = smu_dpm_clks->dpm_clks;
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
smu_dpm_clks->mc_address.high_part);
smu_dpm_clks->mc_address.low_part);
struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
&smu_dpm_clks.mc_address.quad_part);
if (smu_dpm_clks.dpm_clks == NULL) {
smu_dpm_clks.dpm_clks = &dummy_clocks;
smu_dpm_clks.mc_address.quad_part = 0;
ASSERT(smu_dpm_clks.dpm_clks);
dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
smu_dpm_clks.dpm_clks->MinGfxClk,
smu_dpm_clks.dpm_clks->MaxGfxClk);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
smu_dpm_clks.dpm_clks->DcfClocks[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
i, smu_dpm_clks.dpm_clks->DispClocks[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
i, smu_dpm_clks.dpm_clks->SocClocks[i]);
i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
smu_dpm_clks.dpm_clks);
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
smu_dpm_clks.dpm_clks);
smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
smu_dpm_clks.dpm_clks->MinGfxClk,
smu_dpm_clks.dpm_clks->MaxGfxClk);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
smu_dpm_clks.dpm_clks->DcfClocks[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
i, smu_dpm_clks.dpm_clks->DispClocks[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
i, smu_dpm_clks.dpm_clks->SocClocks[i]);
i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
smu_dpm_clks.dpm_clks);
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
smu_dpm_clks.dpm_clks);
struct dcn314_smu_dpm_clks *smu_dpm_clks)
DpmClocks314_t *table = smu_dpm_clks->dpm_clks;
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
smu_dpm_clks->mc_address.high_part);
smu_dpm_clks->mc_address.low_part);
struct dcn314_smu_dpm_clks smu_dpm_clks = { 0 };
smu_dpm_clks.dpm_clks = (DpmClocks314_t *)dm_helpers_allocate_gpu_mem(
&smu_dpm_clks.mc_address.quad_part);
if (smu_dpm_clks.dpm_clks == NULL) {
smu_dpm_clks.dpm_clks = &dummy_clocks;
smu_dpm_clks.mc_address.quad_part = 0;
ASSERT(smu_dpm_clks.dpm_clks);
dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
struct dcn315_smu_dpm_clks *smu_dpm_clks)
DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
smu_dpm_clks->mc_address.high_part);
smu_dpm_clks->mc_address.low_part);
struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(
&smu_dpm_clks.mc_address.quad_part);
if (smu_dpm_clks.dpm_clks == NULL) {
smu_dpm_clks.dpm_clks = &dummy_clocks;
smu_dpm_clks.mc_address.quad_part = 0;
ASSERT(smu_dpm_clks.dpm_clks);
dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
smu_dpm_clks.dpm_clks->MinGfxClk,
smu_dpm_clks.dpm_clks->MaxGfxClk);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
smu_dpm_clks.dpm_clks->DcfClocks[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
i, smu_dpm_clks.dpm_clks->DispClocks[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
i, smu_dpm_clks.dpm_clks->SocClocks[i]);
i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
smu_dpm_clks.dpm_clks);
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
smu_dpm_clks.dpm_clks);
struct dcn316_smu_dpm_clks *smu_dpm_clks)
DpmClocks_316_t *table = smu_dpm_clks->dpm_clks;
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
smu_dpm_clks->mc_address.high_part);
smu_dpm_clks->mc_address.low_part);
struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };
smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem(
&smu_dpm_clks.mc_address.quad_part);
if (smu_dpm_clks.dpm_clks == NULL) {
smu_dpm_clks.dpm_clks = &dummy_clocks;
smu_dpm_clks.mc_address.quad_part = 0;
ASSERT(smu_dpm_clks.dpm_clks);
dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
smu_dpm_clks.dpm_clks);
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
smu_dpm_clks.dpm_clks);
struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
&smu_dpm_clks.mc_address.quad_part);
if (smu_dpm_clks.dpm_clks == NULL) {
smu_dpm_clks.dpm_clks = &dummy_clocks;
smu_dpm_clks.mc_address.quad_part = 0;
ASSERT(smu_dpm_clks.dpm_clks);
translate_to_DpmClocks_t_dcn35(&smu_dpm_clks_dcn351, &smu_dpm_clks);
dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
smu_dpm_clks.dpm_clks->MinGfxClk,
smu_dpm_clks.dpm_clks->MaxGfxClk);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
smu_dpm_clks.dpm_clks->DcfClocks[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
i, smu_dpm_clks.dpm_clks->DispClocks[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
i, smu_dpm_clks.dpm_clks->SocClocks[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
smu_dpm_clks.dpm_clks);
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
smu_dpm_clks.dpm_clks);
struct dcn35_smu_dpm_clks *smu_dpm_clks)
DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
smu_dpm_clks->mc_address.high_part);
smu_dpm_clks->mc_address.low_part);
struct dcn351_smu_dpm_clks *smu_dpm_clks)
DpmClocks_t_dcn351 *table = smu_dpm_clks->dpm_clks;
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
smu_dpm_clks->mc_address.high_part);
smu_dpm_clks->mc_address.low_part);