smmu_v3_read_4
uint32_t smmu_v3_read_4(struct smmu_softc *, bus_size_t);
reg = smmu_v3_read_4(sc, SMMU_V3_IDR0);
reg = smmu_v3_read_4(sc, SMMU_V3_IDR1);
reg = smmu_v3_read_4(sc, SMMU_V3_IDR5);
reg = smmu_v3_read_4(sc, SMMU_V3_IDR3);
if (smmu_v3_read_4(sc, SMMU_V3_CR0) & SMMU_V3_CR0_SMMUEN) {
reg = smmu_v3_read_4(sc, SMMU_V3_GBPA);
if (!(smmu_v3_read_4(sc, SMMU_V3_GBPA) & SMMU_V3_GBPA_UPDATE))
smmu_v3_read_4(sc, SMMU_V3_CR0) | SMMU_V3_CR0_EVENTQEN);
smmu_v3_read_4(sc, SMMU_V3_CR0) | SMMU_V3_CR0_PRIQEN);
smmu_v3_read_4(sc, SMMU_V3_CR0) | SMMU_V3_CR0_SMMUEN);
prod = smmu_v3_read_4(sc, SMMU_V3_EVENTQ_PROD);
gerror = smmu_v3_read_4(sc, SMMU_V3_GERROR);
gerrorn = smmu_v3_read_4(sc, SMMU_V3_GERRORN);
uint32_t cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);
prod = smmu_v3_read_4(sc, SMMU_V3_PRIQ_PROD);
if (smmu_v3_read_4(sc, ack_off) == val)
sq->sq_cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);
sq->sq_cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);
sq->sq_cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);
sq->sq_cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);
sq->sq_cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);
sq->sq_cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);
sq->sq_cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);
sq->sq_cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);
sq->sq_cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);