sys/arch/arm64/dev/smmu.c

299

smmu_gr0_write_4(sc, SMMU_SGFSR, smmu_gr0_read_4(sc, SMMU_SGFSR));

sys/arch/arm64/dev/smmu.c

313

smmu_gr0_write_4(sc, SMMU_S2CR(i),

sys/arch/arm64/dev/smmu.c

317

smmu_gr0_write_4(sc, SMMU_S2CR(i),

sys/arch/arm64/dev/smmu.c

324

smmu_gr0_write_4(sc, SMMU_S2CR(i), SMMU_S2CR_TYPE_FAULT);

sys/arch/arm64/dev/smmu.c

327

smmu_gr0_write_4(sc, SMMU_S2CR(i), SMMU_S2CR_TYPE_BYPASS);

sys/arch/arm64/dev/smmu.c

331

smmu_gr0_write_4(sc, SMMU_SMR(i), 0);

sys/arch/arm64/dev/smmu.c

342

smmu_gr0_write_4(sc, SMMU_TLBIALLH, ~0);

sys/arch/arm64/dev/smmu.c

343

smmu_gr0_write_4(sc, SMMU_TLBIALLNSNH, ~0);

sys/arch/arm64/dev/smmu.c

351

smmu_gr0_write_4(sc, SMMU_SACR, reg);

sys/arch/arm64/dev/smmu.c

379

smmu_gr0_write_4(sc, SMMU_SCR0, reg);

sys/arch/arm64/dev/smmu.c

403

smmu_gr0_write_4(sc, SMMU_SGFSR, reg);

sys/arch/arm64/dev/smmu.c

435

smmu_gr0_write_4(sc, SMMU_STLBGSYNC, ~0);

sys/arch/arm64/dev/smmu.c

67

void smmu_gr0_write_4(struct smmu_softc *, bus_size_t, uint32_t);

sys/arch/arm64/dev/smmu.c

824

smmu_gr0_write_4(sc, SMMU_S2CR(dom->sd_smr_idx), reg);

sys/arch/arm64/dev/smmu.c

832

smmu_gr0_write_4(sc, SMMU_SMR(dom->sd_smr_idx), reg);