sys/arch/arm64/dev/smmu.c

162

reg = smmu_gr0_read_4(sc, SMMU_IDR0);

sys/arch/arm64/dev/smmu.c

191

reg = smmu_gr0_read_4(sc, SMMU_IDR1);

sys/arch/arm64/dev/smmu.c

205

reg = smmu_gr0_read_4(sc, SMMU_IDR2);

sys/arch/arm64/dev/smmu.c

299

smmu_gr0_write_4(sc, SMMU_SGFSR, smmu_gr0_read_4(sc, SMMU_SGFSR));

sys/arch/arm64/dev/smmu.c

304

smmu_gr0_read_4(sc, SMMU_SMR(i)) & SMMU_SMR_VALID) {

sys/arch/arm64/dev/smmu.c

305

reg = smmu_gr0_read_4(sc, SMMU_SMR(i));

sys/arch/arm64/dev/smmu.c

346

reg = smmu_gr0_read_4(sc, SMMU_SACR);

sys/arch/arm64/dev/smmu.c

347

if (SMMU_IDR7_MAJOR(smmu_gr0_read_4(sc, SMMU_IDR7)) >= 2)

sys/arch/arm64/dev/smmu.c

360

reg = smmu_gr0_read_4(sc, SMMU_SCR0);

sys/arch/arm64/dev/smmu.c

393

reg = smmu_gr0_read_4(sc, SMMU_SGFSR);

sys/arch/arm64/dev/smmu.c

399

smmu_gr0_read_4(sc, SMMU_SGFSYNR0),

sys/arch/arm64/dev/smmu.c

400

smmu_gr0_read_4(sc, SMMU_SGFSYNR1),

sys/arch/arm64/dev/smmu.c

401

smmu_gr0_read_4(sc, SMMU_SGFSYNR2));

sys/arch/arm64/dev/smmu.c

437

if ((smmu_gr0_read_4(sc, SMMU_STLBGSTATUS) &

sys/arch/arm64/dev/smmu.c

66

uint32_t smmu_gr0_read_4(struct smmu_softc *, bus_size_t);