sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

46

DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

47

DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

48

DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

49

DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

50

DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_REF_DIV, BL_PWM_REF_DIV, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

51

DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

52

DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

53

DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

54

DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

55

DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_EN, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

56

DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

57

DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

58

DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)