DCLK
ps->uvd_clocks.DCLK = le32_to_cpu(pnon_clock_info->ulDCLK);
ps->uvd_clocks.DCLK = 0;
smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
power_state->uvd_clocks.DCLK = 0;
ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
power_state->uvd_clocks.DCLK = 0;
vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
uint32_t DCLK;
CLK_MAP(DCLK, PPCLK_DCLK),
CLK_MAP(DCLK, PPCLK_DCLK),
CLK_MAP(DCLK, PPCLK_DCLK_0),
CLK_MAP(DCLK, CLOCK_DCLK),
CLK_MAP(DCLK, PPCLK_DCLK),
CLK_MAP(DCLK, PPCLK_DCLK_0),
CLK_MAP(DCLK, PPCLK_DCLK),
CLK_MAP(DCLK, PPCLK_DCLK_0),
CLK_MAP(DCLK, PPCLK_DCLK_0),
intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf;