Symbol: DCCG_SRII
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
33
DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
34
DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
35
DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
36
DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
38
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
39
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
44
DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
45
DCCG_SRII(DTO_PARAM, DPPCLK, 5),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
46
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
47
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
48
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
49
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
34
DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
35
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
36
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
37
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
38
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
33
DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
34
DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
35
DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
36
DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn302/dcn302_dccg.h
34
DCCG_SRII(DTO_PARAM, DPPCLK, 4)
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
34
DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
35
DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
38
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
39
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
33
DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
34
DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
35
DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
36
DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
37
DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
47
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
48
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
49
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
50
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
51
DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
52
DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
53
DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
54
DCCG_SRII(MODULO, DTBCLK_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
55
DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
56
DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
57
DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
58
DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
38
DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
39
DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
40
DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
41
DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
42
DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
52
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
53
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
54
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
55
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
56
DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
57
DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
58
DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
59
DCCG_SRII(MODULO, DTBCLK_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
60
DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
61
DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
62
DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
63
DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1239
SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1240
DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1241
DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1246
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1247
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1248
DCCG_SRII(MODULO, DTBCLK_DTO, 0), DCCG_SRII(MODULO, DTBCLK_DTO, 1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1249
DCCG_SRII(MODULO, DTBCLK_DTO, 2), DCCG_SRII(MODULO, DTBCLK_DTO, 3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1250
DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1251
DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
623
SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
624
DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
625
DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
630
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
631
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
635
DCCG_SRII(MODULO, DP_DTO, 0), DCCG_SRII(MODULO, DP_DTO, 1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
636
DCCG_SRII(MODULO, DP_DTO, 2), DCCG_SRII(MODULO, DP_DTO, 3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
637
DCCG_SRII(PHASE, DP_DTO, 0), DCCG_SRII(PHASE, DP_DTO, 1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
638
DCCG_SRII(PHASE, DP_DTO, 2), DCCG_SRII(PHASE, DP_DTO, 3), \