Symbol: DCCG_SFII
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
100
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
101
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
102
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
110
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
111
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
112
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
113
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh)
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
81
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
82
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
83
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
84
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
95
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
96
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
97
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
98
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
99
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
59
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
60
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
61
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
62
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
113
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
114
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
115
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
116
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
117
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
118
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
119
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
120
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
121
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
122
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
123
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
124
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
125
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
126
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
127
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
128
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
129
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
130
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
131
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
132
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
111
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
112
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
113
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
114
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
115
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
116
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
117
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
118
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
119
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
120
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
121
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
122
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
123
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
124
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
125
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
126
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
80
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
81
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
82
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
83
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
84
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
85
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
86
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
87
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
88
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
89
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
90
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
91
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
92
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
93
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
94
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
95
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
102
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
103
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
104
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
105
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
106
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
107
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
108
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
109
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
110
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
111
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
112
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
113
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
114
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
115
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
116
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
117
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
127
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
128
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
129
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
130
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
108
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
109
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
110
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
111
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
112
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
113
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
114
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
115
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
77
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
78
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
79
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
80
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
81
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
82
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
83
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
84
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\