lib/libcrypto/bn/bn_gcd.c

119

int shifts = 0;

lib/libcrypto/bn/bn_gcd.c

139

shifts++;

lib/libcrypto/bn/bn_gcd.c

150

if (shifts) {

lib/libcrypto/bn/bn_gcd.c

151

if (!BN_lshift(a, a, shifts))

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1329

const struct dce_audio_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1345

audio->shifts = shifts;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1355

const struct dce_audio_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1371

audio->shifts = shifts;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

44

aud->shifts->field_name, aud->masks->field_name

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

143

const struct dce_audio_shift *shifts;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

151

const struct dce_audio_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

159

const struct dce_audio_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

38

dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

670

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

677

dce_i2c_hw->shifts = shifts;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

693

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

700

shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

710

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

717

shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

727

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

734

shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

744

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

751

shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

301

const struct dce_i2c_shift *shifts;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

310

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

318

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

326

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

334

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

342

const struct dce_i2c_shift *shifts,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

37

dce_mi->shifts->field_name, dce_mi->masks->field_name

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

966

dce_mi->shifts = mi_shift;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

427

const struct dce_mem_input_shift *shifts;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

39

reg->shifts.field_name, reg->masks.field_name

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

70

struct xfer_func_shift shifts;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

85

struct cm_color_matrix_shift shifts;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

39

vmid->shifts->field_name, vmid->masks->field_name

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

71

const struct dcn20_vmid_shift *shifts;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

41

reg->shifts.field_name, reg->masks.field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

118

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

120

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

196

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

198

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

281

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

283

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

328

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

330

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

332

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

334

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

337

reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

339

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

341

reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

343

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

345

reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

347

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

355

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

357

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

359

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

361

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

364

reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

366

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

368

reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

370

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

372

reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

374

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

538

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

540

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

189

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

191

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

250

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

252

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

339

icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

341

icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

417

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

419

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

421

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

423

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

426

reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

428

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

430

reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

432

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

434

reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

436

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

134

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

136

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

671

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

673

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

675

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

677

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

680

reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

682

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

684

reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

686

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

688

reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

690

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

173

reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

175

reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

178

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

180

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

182

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

184

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

187

reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

189

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

191

reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

193

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

195

reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

197

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

341

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

343

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

421

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

423

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

199

cur_matrix_regs.shifts.csc_c11 = dpp->tf_shift->CUR0_MATRIX_C11_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

201

cur_matrix_regs.shifts.csc_c12 = dpp->tf_shift->CUR0_MATRIX_C12_A;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

45

struct DCN3_xfer_func_shift shifts;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

318

gam_regs.shifts.csc_c11 = dwbc30->dwbc_shift->DWB_GAMUT_REMAPA_C11;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

320

gam_regs.shifts.csc_c12 = dwbc30->dwbc_shift->DWB_GAMUT_REMAPA_C12;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

52

reg->shifts.field_region_start_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

54

reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

57

reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

59

reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

61

reg->shifts.exp_region1_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

63

reg->shifts.exp_region1_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

66

reg->shifts.field_region_end = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

68

reg->shifts.field_region_end_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

70

reg->shifts.field_region_end_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

72

reg->shifts.field_region_linear_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

74

reg->shifts.exp_region_start = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

76

reg->shifts.exp_resion_start_segment = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

132

ddc->shifts = &ddc_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

142

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

149

ddc->shifts = &ddc_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

159

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

136

ddc->shifts = &ddc_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

146

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

136

ddc->shifts = &ddc_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

146

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

156

generic->shifts = &generic_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

181

ddc->shifts = &ddc_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

191

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

201

ddc->shifts = &ddc_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

211

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

221

generic->shifts = &generic_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

164

generic->shifts = &generic_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

189

ddc->shifts = &ddc_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

199

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

195

generic->shifts = &generic_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

220

ddc->shifts = &ddc_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

230

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

185

generic->shifts = &generic_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

210

ddc->shifts = &ddc_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

220

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

197

generic->shifts = &generic_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

222

ddc->shifts = &ddc_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

232

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

189

generic->shifts = &generic_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

214

ddc->shifts = &ddc_shift[en];

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

224

hpd->shifts = &hpd_shift;

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

39

ddc->shifts->field_name, ddc->masks->field_name

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.h

34

const struct ddc_sh_mask *shifts;

sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c

40

generic->shifts->field_name, generic->masks->field_name

sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.h

35

const struct generic_sh_mask *shifts;

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c

38

hpd->shifts->field_name, hpd->masks->field_name

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.h

34

const struct hpd_sh_mask *shifts;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

40

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

939

hubbub1->shifts = hubbub_shift;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

467

const struct dcn_hubbub_shift *shifts;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

39

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

49

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

687

hubbub->shifts = hubbub_shift;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h

85

const struct dcn_hubbub_shift *shifts;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

102

hubbub->shifts = hubbub_shift;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

41

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

51

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

40

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

50

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

718

hubbub->shifts = hubbub_shift;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

41

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

502

hubbub3->shifts = hubbub_shift;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c

38

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c

48

hubbub1->shifts->field_name, hubbub1->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c

79

hubbub3->shifts = hubbub_shift;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

42

hubbub2->shifts->field_name, hubbub2->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

1056

hubbub2->shifts = hubbub_shift;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

43

hubbub2->shifts->field_name, hubbub2->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

45

hubbub2->shifts->field_name, hubbub2->masks->field_name

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

608

hubbub2->shifts = hubbub_shift;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1266

hubbub2->shifts = hubbub_shift;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

42

hubbub2->shifts->field_name, hubbub2->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

38

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

98

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

48

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

73

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

72

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

54

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

49

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

70

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_hwseq.c

40

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

42

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

43

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

68

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

70

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

67

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

74

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

52

hws->shifts->field_name, hws->masks->field_name

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

194

const struct dce_hwseq_shift *shifts;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

164

ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

166

ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

222

ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

224

ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

250

reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

252

reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

254

reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

256

reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

258

reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

260

reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

262

reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

264

reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

266

reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

268

reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1094

gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1096

gam_regs.shifts.csc_c12 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1170

gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1172

gam_regs.shifts.csc_c12 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1324

ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1326

ocsc_regs.shifts.csc_c12 = mpc30->mpc_shift->MPC_OCSC_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1366

ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1368

ocsc_regs.shifts.csc_c12 = mpc30->mpc_shift->MPC_OCSC_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

207

reg->shifts.field_region_start_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

209

reg->shifts.field_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_OFFSET_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

212

reg->shifts.exp_region0_lut_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

214

reg->shifts.exp_region0_num_segments = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

216

reg->shifts.exp_region1_lut_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

218

reg->shifts.exp_region1_num_segments = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

221

reg->shifts.field_region_end = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

223

reg->shifts.field_region_end_slope = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

225

reg->shifts.field_region_end_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

227

reg->shifts.field_region_linear_slope = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

229

reg->shifts.exp_region_start = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

231

reg->shifts.exp_resion_start_segment = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

143

reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

145

reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

147

reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

149

reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

152

reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

154

reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

156

reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

158

reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

160

reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

162

reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

309

gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

311

gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

343

gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

345

gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

378

gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

380

gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_MCM_SECOND_GAMUT_REMAP_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

475

gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

477

gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

498

gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

500

gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C12_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

521

gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

523

gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_MCM_SECOND_GAMUT_REMAP_C12_A;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

515

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

568

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

544

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

817

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

831

hws->shifts = &dce121_hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

631

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

637

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

852

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1038

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

873

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

891

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1017

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1175

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1053

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

881

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1024

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

836

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

270

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

479

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

266

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

463

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1047

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1330

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1105

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1389

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1045

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1330

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1039

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1326

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1336

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

881

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1317

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

875

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1021

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1399

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1001

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1379

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1002

vmid->shifts = &vmid_shifts;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1380

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1332

hws->shifts = &hwseq_shift;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

874

vmid->shifts = &vmid_shifts;

sys/dev/pci/pccbb.c

1643

int shifts = 0;

sys/dev/pci/pccbb.c

1646

++shifts;

sys/dev/pci/pccbb.c

1649

mask = (1 << shifts);

usr.bin/yacc/defs.h

174

typedef struct shifts shifts;

usr.bin/yacc/defs.h

176

struct shifts *next;

usr.bin/yacc/defs.h

273

extern shifts *first_shift;

usr.bin/yacc/defs.h

277

extern shifts **shift_table;

usr.bin/yacc/lalr.c

129

shifts *sp;

usr.bin/yacc/lalr.c

131

shift_table = NEW2(nstates, shifts *);

usr.bin/yacc/lalr.c

206

shifts *sp;

usr.bin/yacc/lalr.c

291

shifts *sp;

usr.bin/yacc/lalr.c

354

shifts *sp;

usr.bin/yacc/lalr.c

49

shifts **shift_table;

usr.bin/yacc/lr0.c

332

shifts *p;

usr.bin/yacc/lr0.c

335

p = allocate(sizeof(shifts) + (nshifts - 1) * sizeof(short));

usr.bin/yacc/lr0.c

44

shifts *first_shift;

usr.bin/yacc/lr0.c

66

static shifts *last_shift;

usr.bin/yacc/mkpar.c

100

shifts *sp;

usr.bin/yacc/mkpar.c

191

shifts *p;

usr.bin/yacc/output.c

1173

shifts *sp, *next;

usr.bin/yacc/verbose.c

258

shifts *sp;

usr.bin/yacc/verbose.c

338

shifts *sp;

usr.sbin/nsd/options.c

2687

uint8_t shifts[] = {0x0, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff};

usr.sbin/nsd/options.c

2688

*addr_bytes = shifts[subnet_bits];