sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1495

u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1511

sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1512

sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1530

sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1598

u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1721

RREG32(sdma_v6_0_get_reg_offset(adev, i,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

232

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

235

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

400

rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

402

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

403

ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

405

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

436

f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

439

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

466

f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

468

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

494

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

498

rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

506

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

510

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

511

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

512

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

513

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

515

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

516

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

517

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

518

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

522

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

524

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

528

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

530

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

537

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

538

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

544

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

547

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

548

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

551

doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

552

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

561

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

562

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

573

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

576

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

580

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

583

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

586

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

589

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

595

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

599

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

602

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

607

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

609

ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

615

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

693

WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

698

WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

708

WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

713

WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

727

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

732

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

735

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

744

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

749

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

752

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

768

tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

770

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

771

tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

774

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

776

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

879

m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,