sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

764

funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

785

funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

801

funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

522

if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

523

pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges);

sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h

113

void (*set_wm_ranges)(struct pp_smu *pp,

sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h

218

enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,

sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h

282

enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,

sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h

301

enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1379

if (!pp || !pp->set_wm_ranges)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1426

pp->set_wm_ranges(&pp->pp_smu, &ranges);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2606

if (pool->base.pp_smu && pool->base.pp_smu->nv_funcs.set_wm_ranges)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2607

pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1363

pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1557

if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1558

set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);