lib/libc/arch/aarch64/gen/_atomic_lock.c
38
uint32_t scratch = 0;
lib/libc/arch/aarch64/gen/_atomic_lock.c
44
: "+r" (old), "+r" (lock), "+r" (scratch)
lib/libc/arch/arm/gen/_atomic_lock.c
38
uint32_t scratch = 0;
lib/libc/arch/arm/gen/_atomic_lock.c
44
: "+r" (old), "+r" (lock), "+r" (scratch)
lib/libcrypto/modes/ccm128.c
189
} scratch;
lib/libcrypto/modes/ccm128.c
226
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
229
temp.u[0] ^= scratch.u[0];
lib/libcrypto/modes/ccm128.c
230
temp.u[1] ^= scratch.u[1];
lib/libcrypto/modes/ccm128.c
233
((uint64_t *)out)[0] = scratch.u[0] ^ ((uint64_t *)inp)[0];
lib/libcrypto/modes/ccm128.c
234
((uint64_t *)out)[1] = scratch.u[1] ^ ((uint64_t *)inp)[1];
lib/libcrypto/modes/ccm128.c
245
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
247
out[i] = scratch.c[i] ^ inp[i];
lib/libcrypto/modes/ccm128.c
253
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
254
ctx->cmac.u[0] ^= scratch.u[0];
lib/libcrypto/modes/ccm128.c
255
ctx->cmac.u[1] ^= scratch.u[1];
lib/libcrypto/modes/ccm128.c
276
} scratch;
lib/libcrypto/modes/ccm128.c
300
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
304
ctx->cmac.u[0] ^= (scratch.u[0] ^= temp.u[0]);
lib/libcrypto/modes/ccm128.c
305
ctx->cmac.u[1] ^= (scratch.u[1] ^= temp.u[1]);
lib/libcrypto/modes/ccm128.c
306
memcpy(out, scratch.c, 16);
lib/libcrypto/modes/ccm128.c
308
ctx->cmac.u[0] ^= (((uint64_t *)out)[0] = scratch.u[0] ^
lib/libcrypto/modes/ccm128.c
310
ctx->cmac.u[1] ^= (((uint64_t *)out)[1] = scratch.u[1] ^
lib/libcrypto/modes/ccm128.c
321
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
323
ctx->cmac.c[i] ^= (out[i] = scratch.c[i] ^ inp[i]);
lib/libcrypto/modes/ccm128.c
330
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
331
ctx->cmac.u[0] ^= scratch.u[0];
lib/libcrypto/modes/ccm128.c
332
ctx->cmac.u[1] ^= scratch.u[1];
lib/libcrypto/modes/ccm128.c
368
} scratch;
lib/libcrypto/modes/ccm128.c
404
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
406
out[i] = scratch.c[i] ^ inp[i];
lib/libcrypto/modes/ccm128.c
412
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
413
ctx->cmac.u[0] ^= scratch.u[0];
lib/libcrypto/modes/ccm128.c
414
ctx->cmac.u[1] ^= scratch.u[1];
lib/libcrypto/modes/ccm128.c
435
} scratch;
lib/libcrypto/modes/ccm128.c
463
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
465
ctx->cmac.c[i] ^= (out[i] = scratch.c[i] ^ inp[i]);
lib/libcrypto/modes/ccm128.c
472
(*block)(ctx->nonce.c, scratch.c, key);
lib/libcrypto/modes/ccm128.c
473
ctx->cmac.u[0] ^= scratch.u[0];
lib/libcrypto/modes/ccm128.c
474
ctx->cmac.u[1] ^= scratch.u[1];
lib/libcrypto/modes/xts128.c
127
out[i] = scratch.c[i];
lib/libcrypto/modes/xts128.c
128
scratch.c[i] = ch;
lib/libcrypto/modes/xts128.c
130
scratch.u[0] ^= tweak.u[0];
lib/libcrypto/modes/xts128.c
131
scratch.u[1] ^= tweak.u[1];
lib/libcrypto/modes/xts128.c
132
(*ctx->block1)(scratch.c, scratch.c, ctx->key1);
lib/libcrypto/modes/xts128.c
133
scratch.u[0] ^= tweak.u[0];
lib/libcrypto/modes/xts128.c
134
scratch.u[1] ^= tweak.u[1];
lib/libcrypto/modes/xts128.c
135
memcpy(out - 16, scratch.c, 16);
lib/libcrypto/modes/xts128.c
161
memcpy(scratch.c, inp, 16);
lib/libcrypto/modes/xts128.c
162
scratch.u[0] ^= tweak1.u[0];
lib/libcrypto/modes/xts128.c
163
scratch.u[1] ^= tweak1.u[1];
lib/libcrypto/modes/xts128.c
165
scratch.u[0] = ((uint64_t *)inp)[0] ^ tweak1.u[0];
lib/libcrypto/modes/xts128.c
166
scratch.u[1] = ((uint64_t *)inp)[1] ^ tweak1.u[1];
lib/libcrypto/modes/xts128.c
168
(*ctx->block1)(scratch.c, scratch.c, ctx->key1);
lib/libcrypto/modes/xts128.c
169
scratch.u[0] ^= tweak1.u[0];
lib/libcrypto/modes/xts128.c
170
scratch.u[1] ^= tweak1.u[1];
lib/libcrypto/modes/xts128.c
174
out[16 + i] = scratch.c[i];
lib/libcrypto/modes/xts128.c
175
scratch.c[i] = ch;
lib/libcrypto/modes/xts128.c
177
scratch.u[0] ^= tweak.u[0];
lib/libcrypto/modes/xts128.c
178
scratch.u[1] ^= tweak.u[1];
lib/libcrypto/modes/xts128.c
179
(*ctx->block1)(scratch.c, scratch.c, ctx->key1);
lib/libcrypto/modes/xts128.c
181
scratch.u[0] ^= tweak.u[0];
lib/libcrypto/modes/xts128.c
182
scratch.u[1] ^= tweak.u[1];
lib/libcrypto/modes/xts128.c
183
memcpy(out, scratch.c, 16);
lib/libcrypto/modes/xts128.c
185
((uint64_t *)out)[0] = scratch.u[0] ^ tweak.u[0];
lib/libcrypto/modes/xts128.c
186
((uint64_t *)out)[1] = scratch.u[1] ^ tweak.u[1];
lib/libcrypto/modes/xts128.c
67
} tweak, scratch;
lib/libcrypto/modes/xts128.c
82
memcpy(scratch.c, inp, 16);
lib/libcrypto/modes/xts128.c
83
scratch.u[0] ^= tweak.u[0];
lib/libcrypto/modes/xts128.c
84
scratch.u[1] ^= tweak.u[1];
lib/libcrypto/modes/xts128.c
86
scratch.u[0] = ((uint64_t *)inp)[0] ^ tweak.u[0];
lib/libcrypto/modes/xts128.c
87
scratch.u[1] = ((uint64_t *)inp)[1] ^ tweak.u[1];
lib/libcrypto/modes/xts128.c
89
(*ctx->block1)(scratch.c, scratch.c, ctx->key1);
lib/libcrypto/modes/xts128.c
91
scratch.u[0] ^= tweak.u[0];
lib/libcrypto/modes/xts128.c
92
scratch.u[1] ^= tweak.u[1];
lib/libcrypto/modes/xts128.c
93
memcpy(out, scratch.c, 16);
lib/libcrypto/modes/xts128.c
95
((uint64_t *)out)[0] = scratch.u[0] ^= tweak.u[0];
lib/libcrypto/modes/xts128.c
96
((uint64_t *)out)[1] = scratch.u[1] ^= tweak.u[1];
libexec/login_token/token.c
356
char scratch[9];
libexec/login_token/token.c
358
strlcpy(scratch, hp, sizeof(scratch));
libexec/login_token/token.c
359
cb->ul[0] = strtoul(scratch, NULL, 16);
libexec/login_token/token.c
361
strlcpy(scratch, hp + 8, sizeof(scratch));
libexec/login_token/token.c
362
cb->ul[1] = strtoul(scratch, NULL, 16);
libexec/login_token/token.c
372
char scratch[17];
libexec/login_token/token.c
374
snprintf(scratch, 9, "%8.8x", cb.ul[0]);
libexec/login_token/token.c
375
snprintf(scratch+8, 9, "%8.8x", cb.ul[1]);
libexec/login_token/token.c
376
memcpy(hp, scratch, 16);
sbin/fsdb/fsdb.c
282
while ((elline = el_gets(elptr, &scratch)) != NULL && scratch != 0) {
sbin/unwind/libunbound/iterator/iter_utils.c
1260
neg = (struct ub_packed_rrset_key*)regional_alloc(env->scratch,
sbin/unwind/libunbound/iterator/iter_utils.c
1271
neg->rk.dname = regional_alloc_init(env->scratch, qinfo->qname,
sbin/unwind/libunbound/iterator/iter_utils.c
1279
newd = (struct packed_rrset_data*)regional_alloc_zero(env->scratch,
sbin/unwind/libunbound/iterator/iter_utils.c
963
dp->name, dp->namelen, dclass, env->scratch, *env->now);
sbin/unwind/libunbound/iterator/iter_utils.c
967
regional_free_all(env->scratch);
sbin/unwind/libunbound/iterator/iter_utils.c
970
regional_free_all(env->scratch);
sbin/unwind/libunbound/iterator/iter_utils.c
974
regional_free_all(env->scratch);
sbin/unwind/libunbound/iterator/iterator.c
1524
qstate->region, qstate->env->scratch, 0, dpname,
sbin/unwind/libunbound/iterator/iterator.c
2683
qstate->env->scratch, 0, iq->dp->name,
sbin/unwind/libunbound/iterator/iterator.c
4354
prs = (struct msg_parse*)regional_alloc(qstate->env->scratch,
sbin/unwind/libunbound/iterator/iterator.c
4365
if(parse_packet(pkt, prs, qstate->env->scratch) != LDNS_RCODE_NOERROR) {
sbin/unwind/libunbound/iterator/iterator.c
4371
if(parse_extract_edns_from_response_msg(prs, &edns, qstate->env->scratch) !=
sbin/unwind/libunbound/iterator/iterator.c
4398
qstate->env->scratch, qstate->env, qstate, ie)) {
sbin/unwind/libunbound/iterator/iterator.c
4480
qstate->env->scratch)) {
sbin/unwind/libunbound/libunbound/libworker.c
100
regional_destroy(w->env->scratch);
sbin/unwind/libunbound/libunbound/libworker.c
157
w->env->scratch = regional_create_custom(cfg->msg_buffer_size);
sbin/unwind/libunbound/libunbound/libworker.c
171
if(!w->env->scratch || !w->env->scratch_buffer) {
sbin/unwind/libunbound/libunbound/libworker.c
571
libworker_enter_result(q->res, buf, q->w->env->scratch, s);
sbin/unwind/libunbound/libunbound/libworker.c
633
w->back->udp_buff, w->env->scratch, NULL, NULL, 0, NULL, 0,
sbin/unwind/libunbound/libunbound/libworker.c
635
regional_free_all(w->env->scratch);
sbin/unwind/libunbound/libunbound/libworker.c
644
w->back->udp_buff, w->env->scratch)) {
sbin/unwind/libunbound/libunbound/libworker.c
645
regional_free_all(w->env->scratch);
sbin/unwind/libunbound/libunbound/libworker.c
714
w->back->udp_buff, w->env->scratch, NULL, NULL, 0, NULL, 0,
sbin/unwind/libunbound/libunbound/libworker.c
716
regional_free_all(w->env->scratch);
sbin/unwind/libunbound/libunbound/libworker.c
724
w->back->udp_buff, w->env->scratch)) {
sbin/unwind/libunbound/libunbound/libworker.c
725
regional_free_all(w->env->scratch);
sbin/unwind/libunbound/libunbound/libworker.c
853
w->back->udp_buff, w->env->scratch, NULL, NULL, 0, NULL, 0,
sbin/unwind/libunbound/libunbound/libworker.c
855
regional_free_all(w->env->scratch);
sbin/unwind/libunbound/libunbound/libworker.c
863
w->back->udp_buff, w->env->scratch)) {
sbin/unwind/libunbound/libunbound/libworker.c
864
regional_free_all(w->env->scratch);
sbin/unwind/libunbound/services/authzone.c
1774
env.scratch = regional_create();
sbin/unwind/libunbound/services/authzone.c
1779
if(!env.scratch) {
sbin/unwind/libunbound/services/authzone.c
1788
regional_destroy(env.scratch);
sbin/unwind/libunbound/services/authzone.c
1895
region = env->scratch;
sbin/unwind/libunbound/services/authzone.c
5772
struct regional* temp = env->scratch;
sbin/unwind/libunbound/services/authzone.c
6865
struct regional* temp = env->scratch;
sbin/unwind/libunbound/services/authzone.c
8286
regional_free_all(env->scratch);
sbin/unwind/libunbound/services/authzone.c
8346
regional_free_all(env->scratch);
sbin/unwind/libunbound/services/authzone.c
8403
struct regional* temp = env->scratch;
sbin/unwind/libunbound/services/authzone.c
8492
regional_free_all(env->scratch);
sbin/unwind/libunbound/services/authzone.c
8498
regional_free_all(env->scratch);
sbin/unwind/libunbound/services/authzone.c
8639
regional_free_all(env->scratch);
sbin/unwind/libunbound/services/authzone.c
8645
regional_free_all(env->scratch);
sbin/unwind/libunbound/services/cache/dns.c
1088
&& (msg=tomsg(env, &k, data, region, now, 0, scratch))) {
sbin/unwind/libunbound/services/cache/dns.c
634
struct regional* scratch)
sbin/unwind/libunbound/services/cache/dns.c
706
rrset_array_unlock_touch(env->rrset_cache, scratch, r->ref,
sbin/unwind/libunbound/services/cache/dns.c
946
uint16_t flags, struct regional* region, struct regional* scratch,
sbin/unwind/libunbound/services/cache/dns.c
967
scratch);
sbin/unwind/libunbound/services/cache/dns.h
168
int allow_expired, struct regional* scratch);
sbin/unwind/libunbound/services/cache/dns.h
199
uint16_t flags, struct regional* region, struct regional* scratch,
sbin/unwind/libunbound/services/cache/rrset.c
405
rrset_array_unlock_touch(struct rrset_cache* r, struct regional* scratch,
sbin/unwind/libunbound/services/cache/rrset.c
411
scratch, sizeof(hashvalue_type)*count))) {
sbin/unwind/libunbound/services/cache/rrset.h
206
void rrset_array_unlock_touch(struct rrset_cache* r, struct regional* scratch,
sbin/unwind/libunbound/services/mesh.c
1389
m->s.env->scratch, udp_size, &r->edns,
sbin/unwind/libunbound/services/mesh.c
1580
r->qflags, r_buffer, 0, 1, m->s.env->scratch,
sbin/unwind/libunbound/services/mesh.c
2091
struct regional* region = mstate->s.env->scratch;
sbin/unwind/libunbound/services/mesh.c
2209
mstate->s.env->scratch);
sbin/unwind/libunbound/services/mesh.c
2248
regional_free_all(mstate->s.env->scratch);
sbin/unwind/libunbound/services/mesh.c
356
qstate->env->cfg->serve_expired, qstate->env->scratch);
sbin/unwind/libunbound/services/mesh.c
450
mesh->env->scratch, LDNS_EDE_OTHER,
sbin/unwind/libunbound/services/mesh.c
453
LDNS_RCODE_SERVFAIL, edns, rep, mesh->env->scratch, mesh->env->now_tv))
sbin/unwind/libunbound/services/mesh.c
457
regional_free_all(mesh->env->scratch);
sbin/unwind/libunbound/services/mesh.c
502
LDNS_RCODE_SERVFAIL, edns, rep, mesh->env->scratch, mesh->env->now_tv))
sbin/unwind/libunbound/services/mesh.c
521
NULL, LDNS_RCODE_SERVFAIL, edns, rep, mesh->env->scratch, mesh->env->now_tv))
sbin/unwind/libunbound/services/mesh.c
608
NULL, LDNS_RCODE_SERVFAIL, edns, rep, mesh->env->scratch, mesh->env->now_tv))
sbin/unwind/libunbound/util/module.h
488
struct regional* scratch;
sbin/unwind/libunbound/validator/autotrust.c
2385
qinfo.qname = regional_alloc_init(env->scratch, tp->name, tp->namelen);
sbin/unwind/libunbound/validator/autotrust.c
2478
regional_free_all(env->scratch);
sbin/unwind/libunbound/validator/val_sigcrypt.c
346
digest = regional_alloc(env->scratch, digestlen);
sbin/unwind/libunbound/validator/val_sigcrypt.c
589
sec = dnskey_verify_rrset_sig(env->scratch,
sbin/unwind/libunbound/validator/val_sigcrypt.c
735
sec = dnskey_verify_rrset_sig(env->scratch,
sbin/unwind/libunbound/validator/val_utils.c
436
regional_free_all(env->scratch);
sys/arch/amd64/amd64/bios.c
138
scratch, sizeof(scratch))) != NULL)
sys/arch/amd64/amd64/bios.c
140
fixstring(scratch));
sys/arch/amd64/amd64/bios.c
142
scratch, sizeof(scratch))) != NULL) {
sys/arch/amd64/amd64/bios.c
143
sminfop = fixstring(scratch);
sys/arch/amd64/amd64/bios.c
152
scratch, sizeof(scratch))) != NULL) {
sys/arch/amd64/amd64/bios.c
153
sminfop = fixstring(scratch);
sys/arch/amd64/amd64/bios.c
88
char scratch[64];
sys/arch/amd64/amd64/ghcb.c
235
ghcb->v_sw_scratch = regs->scratch;
sys/arch/amd64/amd64/ghcb.c
322
ghcb_regs.scratch = ghcb_paddr + offsetof(struct ghcb_sa,
sys/arch/amd64/amd64/ghcb.c
328
ghcb_regs.scratch = ghcb_paddr + offsetof(struct ghcb_sa,
sys/arch/amd64/include/ghcb.h
121
uint64_t scratch;
sys/arch/arm/arm/vfp.c
139
uint32_t scratch = 0;
sys/arch/arm/arm/vfp.c
160
: "=&r" (scratch) : "r" (&pcb->pcb_fpstate));
sys/arch/arm/arm/vfp.c
67
uint32_t scratch;
sys/arch/arm/arm/vfp.c
76
: "=&r" (scratch) : "r" (vfpsave));
sys/arch/arm64/dev/smbios.c
182
scratch, sizeof(scratch))) != NULL)
sys/arch/arm64/dev/smbios.c
184
fixstring(scratch));
sys/arch/arm64/dev/smbios.c
186
scratch, sizeof(scratch))) != NULL)
sys/arch/arm64/dev/smbios.c
188
fixstring(scratch));
sys/arch/arm64/dev/smbios.c
190
scratch, sizeof(scratch))) != NULL) {
sys/arch/arm64/dev/smbios.c
191
sminfop = fixstring(scratch);
sys/arch/arm64/dev/smbios.c
78
char scratch[64];
sys/arch/arm64/stand/efiboot/smbios.c
119
scratch, sizeof(scratch))) != NULL)
sys/arch/arm64/stand/efiboot/smbios.c
121
fixstring(scratch));
sys/arch/arm64/stand/efiboot/smbios.c
123
scratch, sizeof(scratch))) != NULL)
sys/arch/arm64/stand/efiboot/smbios.c
125
fixstring(scratch));
sys/arch/arm64/stand/efiboot/smbios.c
127
scratch, sizeof(scratch))) != NULL) {
sys/arch/arm64/stand/efiboot/smbios.c
128
sminfop = fixstring(scratch);
sys/arch/arm64/stand/efiboot/smbios.c
59
char scratch[64];
sys/arch/i386/i386/bios.c
162
char scratch[64], *str;
sys/arch/i386/i386/bios.c
290
scratch, sizeof(scratch))) != NULL)
sys/arch/i386/i386/bios.c
292
fixstring(scratch));
sys/arch/i386/i386/bios.c
294
scratch, sizeof(scratch))) != NULL) {
sys/arch/i386/i386/bios.c
295
sminfop = fixstring(scratch);
sys/arch/i386/i386/bios.c
305
scratch, sizeof(scratch))) != NULL) {
sys/arch/i386/i386/bios.c
306
sminfop = fixstring(scratch);
sys/arch/powerpc/include/cpu.h
345
u_long scratch;
sys/arch/powerpc/include/cpu.h
349
" cmpw 0,%0,%1; bne 1b" : "=r"(tb), "=r"(scratch));
sys/arch/powerpc/powerpc/pmap.c
1603
uint32_t scratch, sdr1;
sys/arch/powerpc/powerpc/pmap.c
1640
: "=r"(scratch) : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
sys/dev/ic/ciss.c
1011
ldid = sc->scratch;
sys/dev/ic/ciss.c
1023
ldstat = sc->scratch;
sys/dev/ic/ciss.c
1051
ldstat = sc->scratch;
sys/dev/ic/ciss.c
1070
pdid = sc->scratch;
sys/dev/ic/ciss.c
1097
blink = sc->scratch;
sys/dev/ic/ciss.c
1138
ldstat = sc->scratch;
sys/dev/ic/ciss.c
1298
pdid = sc->scratch;
sys/dev/ic/ciss.c
299
(caddr_t *)&sc->scratch, BUS_DMA_NOWAIT))) {
sys/dev/ic/ciss.c
305
inq = sc->scratch;
sys/dev/ic/ciss.c
754
lmap = sc->scratch;
sys/dev/ic/ciss.c
800
flush = sc->scratch;
sys/dev/ic/cissvar.h
50
void *scratch;
sys/dev/ic/rtw.c
3689
char scratch[sizeof("unknown 0xXX")];
sys/dev/ic/rtw.c
3792
snprintf(scratch, sizeof(scratch), "unknown 0x%02x", rfchipid);
sys/dev/ic/rtw.c
3793
rfname = scratch;
sys/dev/ic/rtw.c
3839
char scratch[sizeof("unknown 0xXXXXXXXX")];
sys/dev/ic/rtw.c
3867
snprintf(scratch, sizeof(scratch), "unknown 0x%08x",
sys/dev/ic/rtw.c
3869
vername = scratch;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1701
ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1702
if (!ctx->scratch)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1882
kfree(adev->mode_info.atom_context->scratch);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
204
ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
205
if (!ctx->scratch)
sys/dev/pci/drm/amd/amdgpu/atom.c
297
val = gctx->scratch[(gctx->fb_base / 4) + idx];
sys/dev/pci/drm/amd/amdgpu/atom.c
559
gctx->scratch[(gctx->fb_base / 4) + idx] = val;
sys/dev/pci/drm/amd/amdgpu/atom.h
147
uint32_t *scratch;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
75
base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
sys/dev/pci/drm/amd/amdgpu/atombios_i2c.c
54
base = (unsigned char *)adev->mode_info.atom_context->scratch;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4036
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4041
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4050
amdgpu_ring_write(ring, scratch -
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4056
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
566
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
571
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
580
gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
583
amdgpu_ring_write(ring, scratch -
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
590
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
453
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
458
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
468
gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
471
amdgpu_ring_write(ring, scratch -
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
478
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1197
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1202
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1208
amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1213
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
280
dma_addr_t *scratch, u64 ttm_res_offset)
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
295
src = scratch;
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
296
dst = (u64 *)(scratch + npages);
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
400
dma_addr_t *scratch;
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
419
scratch = (dma_addr_t *)(migrate.dst + npages);
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
445
r = svm_migrate_copy_to_vram(node, prange, &migrate, &mfence, scratch, ttm_res_offset);
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
455
svm_range_dma_unmap_dev(adev->dev, scratch, 0, npages);
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
584
dma_addr_t *scratch, u64 npages)
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
599
src = (u64 *)(scratch + npages);
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
600
dst = scratch;
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
698
dma_addr_t *scratch;
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
721
scratch = (dma_addr_t *)(migrate.dst + npages);
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
748
scratch, npages);
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
758
svm_range_dma_unmap_dev(adev->dev, scratch, 0, npages);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2081
memset(dc->scratch.pipes_to_unlock_first, 0, sizeof(dc->scratch.pipes_to_unlock_first));
sys/dev/pci/drm/amd/display/dc/core/dc.c
2094
dc->scratch.pipes_to_unlock_first[i] = true;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3363
struct dc_scratch_space *scratch,
sys/dev/pci/drm/amd/display/dc/core/dc.c
3373
dc_plane_copy_config(&scratch->plane_states[i], status->plane_states[i]);
sys/dev/pci/drm/amd/display/dc/core/dc.c
3375
scratch->stream_state = *stream;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3379
struct dc_scratch_space *scratch,
sys/dev/pci/drm/amd/display/dc/core/dc.c
3389
dc_plane_copy_config(status->plane_states[i], &scratch->plane_states[i]);
sys/dev/pci/drm/amd/display/dc/core/dc.c
3391
*stream = scratch->stream_state;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3482
backup_planes_and_stream_state(&dc->scratch.current_state, stream);
sys/dev/pci/drm/amd/display/dc/core/dc.c
3576
backup_planes_and_stream_state(&dc->scratch.new_state, stream);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4798
restore_planes_and_stream_state(&dc->scratch.current_state, stream);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4828
restore_planes_and_stream_state(&dc->scratch.new_state, stream);
sys/dev/pci/drm/amd/display/dc/dc.h
1774
} scratch;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
966
DC_LOG_DEBUG(" scratch [0] : %08x", dc_dmub_srv->dmub->debug.scratch[0]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
967
DC_LOG_DEBUG(" scratch [1] : %08x", dc_dmub_srv->dmub->debug.scratch[1]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
968
DC_LOG_DEBUG(" scratch [2] : %08x", dc_dmub_srv->dmub->debug.scratch[2]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
969
DC_LOG_DEBUG(" scratch [3] : %08x", dc_dmub_srv->dmub->debug.scratch[3]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
970
DC_LOG_DEBUG(" scratch [4] : %08x", dc_dmub_srv->dmub->debug.scratch[4]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
971
DC_LOG_DEBUG(" scratch [5] : %08x", dc_dmub_srv->dmub->debug.scratch[5]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
972
DC_LOG_DEBUG(" scratch [6] : %08x", dc_dmub_srv->dmub->debug.scratch[6]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
973
DC_LOG_DEBUG(" scratch [7] : %08x", dc_dmub_srv->dmub->debug.scratch[7]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
974
DC_LOG_DEBUG(" scratch [8] : %08x", dc_dmub_srv->dmub->debug.scratch[8]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
975
DC_LOG_DEBUG(" scratch [9] : %08x", dc_dmub_srv->dmub->debug.scratch[9]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
976
DC_LOG_DEBUG(" scratch [10] : %08x", dc_dmub_srv->dmub->debug.scratch[10]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
977
DC_LOG_DEBUG(" scratch [11] : %08x", dc_dmub_srv->dmub->debug.scratch[11]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
978
DC_LOG_DEBUG(" scratch [12] : %08x", dc_dmub_srv->dmub->debug.scratch[12]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
979
DC_LOG_DEBUG(" scratch [13] : %08x", dc_dmub_srv->dmub->debug.scratch[13]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
980
DC_LOG_DEBUG(" scratch [14] : %08x", dc_dmub_srv->dmub->debug.scratch[14]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
981
DC_LOG_DEBUG(" scratch [15] : %08x", dc_dmub_srv->dmub->debug.scratch[15]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2403
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
325
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
592
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
731
struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
234
dc->scratch.update_bw_bounding_box.clock_limits;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
268
dc->scratch.update_bw_bounding_box.clock_limits;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1000
struct CalculatePrefetchSchedule_locals_st *s = &scratch->CalculatePrefetchSchedule_locals;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
186
static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2823
struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2826
struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st *s = &scratch->CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3762
static void CalculateStutterEfficiency(struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4085
static void CalculateSwathAndDETConfiguration(struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
454
struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4598
static void UseMinimumDCFCLK(struct display_mode_lib_scratch_st *scratch, struct UseMinimumDCFCLK_params_st *p)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4600
struct UseMinimumDCFCLK_locals_st *s = &scratch->UseMinimumDCFCLK_locals;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5052
static void CalculateVMRowAndSwath(struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5055
struct CalculateVMRowAndSwath_locals_st *s = &scratch->CalculateVMRowAndSwath_locals;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
573
struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
577
struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6272
struct dml_core_mode_support_locals_st *s = &mode_lib->scratch.dml_core_mode_support_locals;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6273
struct CalculatePrefetchSchedule_params_st *CalculatePrefetchSchedule_params = &mode_lib->scratch.CalculatePrefetchSchedule_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6274
struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st *CalculateWatermarks_params = &mode_lib->scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6414
CalculatePrefetchSchedule(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6708
CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6717
struct dml_core_mode_support_locals_st *s = &mode_lib->scratch.dml_core_mode_support_locals;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6718
struct UseMinimumDCFCLK_params_st *UseMinimumDCFCLK_params = &mode_lib->scratch.UseMinimumDCFCLK_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6719
struct CalculateSwathAndDETConfiguration_params_st *CalculateSwathAndDETConfiguration_params = &mode_lib->scratch.CalculateSwathAndDETConfiguration_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6720
struct CalculateVMRowAndSwath_params_st *CalculateVMRowAndSwath_params = &mode_lib->scratch.CalculateVMRowAndSwath_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7030
CalculateSwathAndDETConfiguration(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7569
CalculateSwathAndDETConfiguration(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7750
CalculateVMRowAndSwath(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8010
UseMinimumDCFCLK(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8293
struct dml_core_mode_programming_locals_st *s = &mode_lib->scratch.dml_core_mode_programming_locals;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8294
struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st *CalculateWatermarks_params = &mode_lib->scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8295
struct CalculateVMRowAndSwath_params_st *CalculateVMRowAndSwath_params = &mode_lib->scratch.CalculateVMRowAndSwath_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8296
struct CalculateSwathAndDETConfiguration_params_st *CalculateSwathAndDETConfiguration_params = &mode_lib->scratch.CalculateSwathAndDETConfiguration_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8297
struct CalculateStutterEfficiency_params_st *CalculateStutterEfficiency_params = &mode_lib->scratch.CalculateStutterEfficiency_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8298
struct CalculatePrefetchSchedule_params_st *CalculatePrefetchSchedule_params = &mode_lib->scratch.CalculatePrefetchSchedule_params;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8556
CalculateSwathAndDETConfiguration(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8762
CalculateVMRowAndSwath(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9052
CalculatePrefetchSchedule(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9473
&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9829
CalculateStutterEfficiency(&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
997
static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1914
struct display_mode_lib_scratch_st scratch;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
404
dml_print("DML: MODE SUPPORT: Host VM or Immediate Flip Supported : %s\n", ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !mode_lib->scratch.dml_core_mode_support_locals.ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j]) ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
405
dml_print("DML: MODE SUPPORT: dram clock change support : %s\n", mode_lib->scratch.dml_core_mode_support_locals.dram_clock_change_support == true ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
406
dml_print("DML: MODE SUPPORT: f_clock change support : %s\n", mode_lib->scratch.dml_core_mode_support_locals.f_clock_change_support == true ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
472
struct pipe_ctx *temp_pipe = &dml_ctx->v21.scratch.temp_pipe;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
212
memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
274
memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
287
dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
320
struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
190
struct dml2_core_scratch *scratch)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
198
memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
199
memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
200
memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
213
scratch->main_stream_index_from_svp_stream_index[stream_index] = stream_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
214
scratch->svp_stream_index_from_main_stream_index[stream_index] = stream_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
222
scratch->main_stream_index_from_svp_stream_index[svp_expanded_display_cfg->num_streams] = stream_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
223
scratch->svp_stream_index_from_main_stream_index[stream_index] = svp_expanded_display_cfg->num_streams;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
236
phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index]];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
238
main_plane, phantom_stream, scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index], main_stream);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
241
scratch->phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg->num_planes] = plane_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
242
scratch->main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg->num_planes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
254
const struct dml2_display_cfg *svp_expanded_display_cfg, struct dml2_display_cfg_programming *programming, struct dml2_core_scratch *scratch)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
284
phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[stream_index]];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
366
main_plane_index = scratch->phantom_plane_index_to_main_plane_index[plane_index];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
412
struct dml2_core_mode_support_locals *l = &core->scratch.mode_support_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
418
expand_implict_subvp(in_out->display_cfg, &l->svp_expanded_display_cfg, &core->scratch);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
543
struct dml2_core_mode_programming_locals *l = &core->scratch.mode_programming_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
554
expand_implict_subvp(in_out->display_cfg, &l->svp_expanded_display_cfg, &core->scratch);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
569
pack_mode_programming_params_with_implicit_subvp(core, in_out->display_cfg, &l->svp_expanded_display_cfg, in_out->programming, &core->scratch);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
637
in_out->programming->informative.voltage_level = in_out->instance->scratch.mode_programming_locals.mode_programming_ex_params.min_clk_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
639
in_out->programming->informative.voltage_level = in_out->instance->scratch.mode_support_locals.mode_support_ex_params.min_clk_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10054
static void CalculateStutterEfficiency(struct dml2_core_internal_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10057
struct dml2_core_calcs_CalculateStutterEfficiency_locals *l = &scratch->CalculateStutterEfficiency_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10351
struct dml2_core_calcs_mode_programming_locals *s = &mode_lib->scratch.dml_core_mode_programming_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10352
struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params *CalculateWatermarks_params = &mode_lib->scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10353
struct dml2_core_calcs_CalculateVMRowAndSwath_params *CalculateVMRowAndSwath_params = &mode_lib->scratch.CalculateVMRowAndSwath_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10354
struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params *CalculateSwathAndDETConfiguration_params = &mode_lib->scratch.CalculateSwathAndDETConfiguration_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10355
struct dml2_core_calcs_CalculateStutterEfficiency_params *CalculateStutterEfficiency_params = &mode_lib->scratch.CalculateStutterEfficiency_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10356
struct dml2_core_calcs_CalculatePrefetchSchedule_params *CalculatePrefetchSchedule_params = &mode_lib->scratch.CalculatePrefetchSchedule_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10357
struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params *CheckGlobalPrefetchAdmissibility_params = &mode_lib->scratch.CheckGlobalPrefetchAdmissibility_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10358
struct dml2_core_calcs_calculate_mcache_setting_params *calculate_mcache_setting_params = &mode_lib->scratch.calculate_mcache_setting_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10359
struct dml2_core_calcs_calculate_tdlut_setting_params *calculate_tdlut_setting_params = &mode_lib->scratch.calculate_tdlut_setting_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10360
struct dml2_core_shared_CalculateMetaAndPTETimes_params *CalculateMetaAndPTETimes_params = &mode_lib->scratch.CalculateMetaAndPTETimes_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10361
struct dml2_core_calcs_calculate_peak_bandwidth_required_params *calculate_peak_bandwidth_params = &mode_lib->scratch.calculate_peak_bandwidth_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10362
struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params *calculate_bytes_to_fetch_required_to_hide_latency_params = &mode_lib->scratch.calculate_bytes_to_fetch_required_to_hide_latency_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10375
memset(&mode_lib->scratch, 0, sizeof(struct dml2_core_internal_scratch));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10627
CalculateSwathAndDETConfiguration(&mode_lib->scratch, CalculateSwathAndDETConfiguration_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10776
CalculateVMRowAndSwath(&mode_lib->scratch, CalculateVMRowAndSwath_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10847
calculate_mcache_setting(&mode_lib->scratch, calculate_mcache_setting_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10911
calculate_tdlut_setting(&mode_lib->scratch, calculate_tdlut_setting_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11163
CheckGlobalPrefetchAdmissibility(&mode_lib->scratch, CheckGlobalPrefetchAdmissibility_params); // dont care about the check output for mode programming
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11299
mode_lib->mp.NoTimeToPrefetch[k] = CalculatePrefetchSchedule(&mode_lib->scratch, CalculatePrefetchSchedule_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11436
&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11494
&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11569
&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11715
CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(&mode_lib->scratch, CalculateWatermarks_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11760
CalculateMetaAndPTETimes_params->scratch = &mode_lib->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11976
CalculateStutterEfficiency(&mode_lib->scratch, CalculateStutterEfficiency_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11989
CalculateStutterEfficiency(&mode_lib->scratch, CalculateStutterEfficiency_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12094
mode_lib->scratch.calculate_vm_and_row_bytes_params.ViewportStationary = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12095
mode_lib->scratch.calculate_vm_and_row_bytes_params.DCCEnable = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12096
mode_lib->scratch.calculate_vm_and_row_bytes_params.NumberOfDPPs = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12097
mode_lib->scratch.calculate_vm_and_row_bytes_params.BlockHeight256Bytes = BlockHeight256Bytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12098
mode_lib->scratch.calculate_vm_and_row_bytes_params.BlockWidth256Bytes = BlockWidth256Bytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12099
mode_lib->scratch.calculate_vm_and_row_bytes_params.SourcePixelFormat = SourcePixelFormat;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12100
mode_lib->scratch.calculate_vm_and_row_bytes_params.SurfaceTiling = SurfaceTiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12101
mode_lib->scratch.calculate_vm_and_row_bytes_params.BytePerPixel = BytePerPixel;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12102
mode_lib->scratch.calculate_vm_and_row_bytes_params.RotationAngle = ScanDirection;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12103
mode_lib->scratch.calculate_vm_and_row_bytes_params.SwathWidth = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12104
mode_lib->scratch.calculate_vm_and_row_bytes_params.ViewportHeight = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12105
mode_lib->scratch.calculate_vm_and_row_bytes_params.ViewportXStart = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12106
mode_lib->scratch.calculate_vm_and_row_bytes_params.ViewportYStart = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12107
mode_lib->scratch.calculate_vm_and_row_bytes_params.GPUVMEnable = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12108
mode_lib->scratch.calculate_vm_and_row_bytes_params.GPUVMMaxPageTableLevels = 4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12109
mode_lib->scratch.calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = GPUVMMinPageSizeKBytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12110
mode_lib->scratch.calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = PTEBufferSizeInRequests;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12111
mode_lib->scratch.calculate_vm_and_row_bytes_params.Pitch = pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12112
mode_lib->scratch.calculate_vm_and_row_bytes_params.MacroTileWidth = MacroTileWidth;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12113
mode_lib->scratch.calculate_vm_and_row_bytes_params.MacroTileHeight = MacroTileHeight;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12114
mode_lib->scratch.calculate_vm_and_row_bytes_params.is_phantom = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12115
mode_lib->scratch.calculate_vm_and_row_bytes_params.DCCMetaPitch = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12116
mode_lib->scratch.calculate_vm_and_row_bytes_params.mrq_present = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12118
mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &dummy_integer[1];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12119
mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &dummy_integer[2];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12120
mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_width_ub = &dummy_integer[3];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12121
mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_height = dpte_row_height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12122
mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_height_linear = &dummy_integer[4];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12123
mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &dummy_integer[5];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12124
mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &dummy_integer[6];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12125
mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &dummy_integer[7];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12126
mode_lib->scratch.calculate_vm_and_row_bytes_params.vmpg_width = &dummy_integer[8];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12127
mode_lib->scratch.calculate_vm_and_row_bytes_params.vmpg_height = &dummy_integer[9];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12128
mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &dummy_integer[11];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12129
mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &dummy_integer[12];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12130
mode_lib->scratch.calculate_vm_and_row_bytes_params.PTERequestSize = &dummy_integer[13];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12131
mode_lib->scratch.calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &dummy_integer[14];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12133
mode_lib->scratch.calculate_vm_and_row_bytes_params.meta_row_bytes = &dummy_integer[15];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12134
mode_lib->scratch.calculate_vm_and_row_bytes_params.MetaRequestWidth = &dummy_integer[16];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12135
mode_lib->scratch.calculate_vm_and_row_bytes_params.MetaRequestHeight = &dummy_integer[17];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12136
mode_lib->scratch.calculate_vm_and_row_bytes_params.meta_row_width = &dummy_integer[18];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12137
mode_lib->scratch.calculate_vm_and_row_bytes_params.meta_row_height = &dummy_integer[19];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12138
mode_lib->scratch.calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &dummy_integer[20];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12141
CalculateVMAndRowBytes(&mode_lib->scratch.calculate_vm_and_row_bytes_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12713
rq_dlg_get_dlg_reg(&mode_lib->scratch, &out->dlg_regs, &out->ttu_regs, display_cfg, mode_lib, pipe_index);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2267
struct dml2_core_internal_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2416
struct dml2_core_internal_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2421
struct dml2_core_shared_calculate_mcache_setting_locals *l = &scratch->calculate_mcache_setting_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2477
calculate_mcache_row_bytes(scratch, &l->l_p);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2513
calculate_mcache_row_bytes(scratch, &l->c_p);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2863
static void CalculateVMRowAndSwath(struct dml2_core_internal_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2866
struct dml2_core_calcs_CalculateVMRowAndSwath_locals *s = &scratch->CalculateVMRowAndSwath_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2888
scratch->calculate_vm_and_row_bytes_params.ViewportStationary = p->myPipe[k].ViewportStationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2889
scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2890
scratch->calculate_vm_and_row_bytes_params.NumberOfDPPs = p->myPipe[k].DPPPerSurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2891
scratch->calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p->myPipe[k].BlockHeight256BytesC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2892
scratch->calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p->myPipe[k].BlockWidth256BytesC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2893
scratch->calculate_vm_and_row_bytes_params.SourcePixelFormat = p->myPipe[k].SourcePixelFormat;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2894
scratch->calculate_vm_and_row_bytes_params.SurfaceTiling = p->myPipe[k].SurfaceTiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2895
scratch->calculate_vm_and_row_bytes_params.BytePerPixel = p->myPipe[k].BytePerPixelC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2896
scratch->calculate_vm_and_row_bytes_params.RotationAngle = p->myPipe[k].RotationAngle;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2897
scratch->calculate_vm_and_row_bytes_params.SwathWidth = p->SwathWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2898
scratch->calculate_vm_and_row_bytes_params.ViewportHeight = p->myPipe[k].ViewportHeightC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2899
scratch->calculate_vm_and_row_bytes_params.ViewportXStart = p->myPipe[k].ViewportXStartC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2900
scratch->calculate_vm_and_row_bytes_params.ViewportYStart = p->myPipe[k].ViewportYStartC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2901
scratch->calculate_vm_and_row_bytes_params.GPUVMEnable = p->display_cfg->gpuvm_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2902
scratch->calculate_vm_and_row_bytes_params.GPUVMMaxPageTableLevels = p->display_cfg->gpuvm_max_page_table_levels;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2903
scratch->calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2904
scratch->calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s->PTEBufferSizeInRequestsForChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2905
scratch->calculate_vm_and_row_bytes_params.Pitch = p->myPipe[k].PitchC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2906
scratch->calculate_vm_and_row_bytes_params.MacroTileWidth = p->myPipe[k].BlockWidthC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2907
scratch->calculate_vm_and_row_bytes_params.MacroTileHeight = p->myPipe[k].BlockHeightC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2908
scratch->calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2909
scratch->calculate_vm_and_row_bytes_params.DCCMetaPitch = p->myPipe[k].DCCMetaPitchC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2910
scratch->calculate_vm_and_row_bytes_params.mrq_present = p->mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2912
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &s->PixelPTEBytesPerRowC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2913
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &s->PixelPTEBytesPerRowStorageC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2914
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub = &p->dpte_row_width_chroma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2915
scratch->calculate_vm_and_row_bytes_params.dpte_row_height = &p->dpte_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2916
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_linear = &p->dpte_row_height_linear_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2917
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &s->PixelPTEBytesPerRowC_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2918
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &s->dpte_row_width_chroma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2919
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &s->dpte_row_height_chroma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2920
scratch->calculate_vm_and_row_bytes_params.vmpg_width = &p->vmpg_width_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2921
scratch->calculate_vm_and_row_bytes_params.vmpg_height = &p->vmpg_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2922
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &p->PixelPTEReqWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2923
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &p->PixelPTEReqHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2924
scratch->calculate_vm_and_row_bytes_params.PTERequestSize = &p->PTERequestSizeC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2925
scratch->calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &p->dpde0_bytes_per_frame_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2927
scratch->calculate_vm_and_row_bytes_params.meta_row_bytes = &s->meta_row_bytes_per_row_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2928
scratch->calculate_vm_and_row_bytes_params.MetaRequestWidth = &p->meta_req_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2929
scratch->calculate_vm_and_row_bytes_params.MetaRequestHeight = &p->meta_req_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2930
scratch->calculate_vm_and_row_bytes_params.meta_row_width = &p->meta_row_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2931
scratch->calculate_vm_and_row_bytes_params.meta_row_height = &p->meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2932
scratch->calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &p->meta_pte_bytes_per_frame_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2934
s->vm_bytes_c = CalculateVMAndRowBytes(&scratch->calculate_vm_and_row_bytes_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2966
scratch->calculate_vm_and_row_bytes_params.ViewportStationary = p->myPipe[k].ViewportStationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2967
scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2968
scratch->calculate_vm_and_row_bytes_params.NumberOfDPPs = p->myPipe[k].DPPPerSurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2969
scratch->calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p->myPipe[k].BlockHeight256BytesY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2970
scratch->calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p->myPipe[k].BlockWidth256BytesY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2971
scratch->calculate_vm_and_row_bytes_params.SourcePixelFormat = p->myPipe[k].SourcePixelFormat;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2972
scratch->calculate_vm_and_row_bytes_params.SurfaceTiling = p->myPipe[k].SurfaceTiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2973
scratch->calculate_vm_and_row_bytes_params.BytePerPixel = p->myPipe[k].BytePerPixelY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2974
scratch->calculate_vm_and_row_bytes_params.RotationAngle = p->myPipe[k].RotationAngle;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2975
scratch->calculate_vm_and_row_bytes_params.SwathWidth = p->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2976
scratch->calculate_vm_and_row_bytes_params.ViewportHeight = p->myPipe[k].ViewportHeight;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2977
scratch->calculate_vm_and_row_bytes_params.ViewportXStart = p->myPipe[k].ViewportXStart;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2978
scratch->calculate_vm_and_row_bytes_params.ViewportYStart = p->myPipe[k].ViewportYStart;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2979
scratch->calculate_vm_and_row_bytes_params.GPUVMEnable = p->display_cfg->gpuvm_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2980
scratch->calculate_vm_and_row_bytes_params.GPUVMMaxPageTableLevels = p->display_cfg->gpuvm_max_page_table_levels;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2981
scratch->calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2982
scratch->calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s->PTEBufferSizeInRequestsForLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2983
scratch->calculate_vm_and_row_bytes_params.Pitch = p->myPipe[k].PitchY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2984
scratch->calculate_vm_and_row_bytes_params.MacroTileWidth = p->myPipe[k].BlockWidthY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2985
scratch->calculate_vm_and_row_bytes_params.MacroTileHeight = p->myPipe[k].BlockHeightY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2986
scratch->calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2987
scratch->calculate_vm_and_row_bytes_params.DCCMetaPitch = p->myPipe[k].DCCMetaPitchY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2988
scratch->calculate_vm_and_row_bytes_params.mrq_present = p->mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2990
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &s->PixelPTEBytesPerRowY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2991
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &s->PixelPTEBytesPerRowStorageY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2992
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub = &p->dpte_row_width_luma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2993
scratch->calculate_vm_and_row_bytes_params.dpte_row_height = &p->dpte_row_height_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2994
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_linear = &p->dpte_row_height_linear_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2995
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &s->PixelPTEBytesPerRowY_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2996
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &s->dpte_row_width_luma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2997
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &s->dpte_row_height_luma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2998
scratch->calculate_vm_and_row_bytes_params.vmpg_width = &p->vmpg_width_y[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2999
scratch->calculate_vm_and_row_bytes_params.vmpg_height = &p->vmpg_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3000
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &p->PixelPTEReqWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3001
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &p->PixelPTEReqHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3002
scratch->calculate_vm_and_row_bytes_params.PTERequestSize = &p->PTERequestSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3003
scratch->calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &p->dpde0_bytes_per_frame_ub_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3005
scratch->calculate_vm_and_row_bytes_params.meta_row_bytes = &s->meta_row_bytes_per_row_ub_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3006
scratch->calculate_vm_and_row_bytes_params.MetaRequestWidth = &p->meta_req_width_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3007
scratch->calculate_vm_and_row_bytes_params.MetaRequestHeight = &p->meta_req_height_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3008
scratch->calculate_vm_and_row_bytes_params.meta_row_width = &p->meta_row_width_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3009
scratch->calculate_vm_and_row_bytes_params.meta_row_height = &p->meta_row_height_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3010
scratch->calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &p->meta_pte_bytes_per_frame_ub_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3012
s->vm_bytes_l = CalculateVMAndRowBytes(&scratch->calculate_vm_and_row_bytes_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3690
static void CalculateSwathAndDETConfiguration(struct dml2_core_internal_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3774
&scratch->CalculateDETBufferSize_locals,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4611
struct dml2_core_internal_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5087
static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch, struct dml2_core_calcs_CalculatePrefetchSchedule_params *p)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5089
struct dml2_core_calcs_CalculatePrefetchSchedule_locals *s = &scratch->CalculatePrefetchSchedule_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5978
static noinline_for_stack bool CheckGlobalPrefetchAdmissibility(struct dml2_core_internal_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5981
struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals *s = &scratch->CheckGlobalPrefetchAdmissibility_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6676
struct dml2_core_internal_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6679
struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals *s = &scratch->CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7289
struct dml2_core_calcs_mode_support_locals *s = &mode_lib->scratch.dml_core_mode_support_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7290
struct dml2_core_calcs_calculate_tdlut_setting_params *calculate_tdlut_setting_params = &mode_lib->scratch.calculate_tdlut_setting_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7291
struct dml2_core_calcs_CalculatePrefetchSchedule_params *CalculatePrefetchSchedule_params = &mode_lib->scratch.CalculatePrefetchSchedule_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7292
struct dml2_core_calcs_calculate_peak_bandwidth_required_params *calculate_peak_bandwidth_params = &mode_lib->scratch.calculate_peak_bandwidth_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7294
struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params *CheckGlobalPrefetchAdmissibility_params = &mode_lib->scratch.CheckGlobalPrefetchAdmissibility_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7296
struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params *CalculateWatermarks_params = &mode_lib->scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7339
calculate_tdlut_setting(&mode_lib->scratch, calculate_tdlut_setting_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7532
mode_lib->ms.NoTimeForPrefetch[k] = CalculatePrefetchSchedule(&mode_lib->scratch, CalculatePrefetchSchedule_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7671
&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7729
mode_lib->ms.support.PrefetchSupported = CheckGlobalPrefetchAdmissibility(&mode_lib->scratch, CheckGlobalPrefetchAdmissibility_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7763
&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7838
&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7920
CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(&mode_lib->scratch, CalculateWatermarks_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7936
struct dml2_core_calcs_mode_support_locals *s = &mode_lib->scratch.dml_core_mode_support_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7937
struct dml2_core_calcs_CalculateVMRowAndSwath_params *CalculateVMRowAndSwath_params = &mode_lib->scratch.CalculateVMRowAndSwath_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7938
struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params *CalculateSwathAndDETConfiguration_params = &mode_lib->scratch.CalculateSwathAndDETConfiguration_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7939
struct dml2_core_calcs_calculate_mcache_setting_params *calculate_mcache_setting_params = &mode_lib->scratch.calculate_mcache_setting_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7940
struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params *calculate_bytes_to_fetch_required_to_hide_latency_params = &mode_lib->scratch.calculate_bytes_to_fetch_required_to_hide_latency_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7943
memset(&mode_lib->scratch, 0, sizeof(struct dml2_core_internal_scratch));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8358
CalculateSwathAndDETConfiguration(&mode_lib->scratch, CalculateSwathAndDETConfiguration_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8426
&mode_lib->scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8846
CalculateSwathAndDETConfiguration(&mode_lib->scratch, CalculateSwathAndDETConfiguration_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8989
CalculateVMRowAndSwath(&mode_lib->scratch, CalculateVMRowAndSwath_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9376
calculate_mcache_setting(&mode_lib->scratch, calculate_mcache_setting_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1648
struct dml2_core_internal_scratch *scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2303
struct dml2_core_internal_scratch scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
609
struct dml2_core_scratch *scratch)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
617
memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
618
memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
619
memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
632
scratch->main_stream_index_from_svp_stream_index[stream_index] = stream_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
633
scratch->svp_stream_index_from_main_stream_index[stream_index] = stream_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
641
scratch->main_stream_index_from_svp_stream_index[svp_expanded_display_cfg->num_streams] = stream_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
642
scratch->svp_stream_index_from_main_stream_index[stream_index] = svp_expanded_display_cfg->num_streams;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
655
phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index]];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
657
main_plane, phantom_stream, scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index], main_stream);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
660
scratch->phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg->num_planes] = plane_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
661
scratch->main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg->num_planes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
33
struct dml2_core_scratch *scratch);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
125
if (pmo->scratch.pmo_dcn3.current_candidate[0] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
126
pmo->scratch.pmo_dcn3.current_candidate[0]--;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
129
for (borrow_from = 1; borrow_from < size && pmo->scratch.pmo_dcn3.current_candidate[borrow_from] == 0; borrow_from++)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
133
pmo->scratch.pmo_dcn3.current_candidate[borrow_from]--;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
135
pmo->scratch.pmo_dcn3.current_candidate[i] = pmo->scratch.pmo_dcn3.reserved_time_candidates_count[i] - 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
538
pmo->scratch.pmo_dcn3.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
539
pmo->scratch.pmo_dcn3.max_latency_index = pmo->mcg_clock_table_size - 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
540
pmo->scratch.pmo_dcn3.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
542
pmo->scratch.pmo_dcn3.stream_mask = 0xF;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
565
pmo->scratch.pmo_dcn3.stream_mask &= ~(0x1 << plane_descriptor->stream_index);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
601
pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][0] = min_reserved_vblank_time;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
602
pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index] = candidate_count;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
604
if (!(pmo->scratch.pmo_dcn3.stream_mask & (0x1 << stream_index)))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
611
if (are_timings_trivially_synchronizable(in_out->base_display_config, pmo->scratch.pmo_dcn3.stream_mask)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
612
pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][candidate_count++] =
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
620
if (are_timings_trivially_synchronizable(in_out->base_display_config, pmo->scratch.pmo_dcn3.stream_mask)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
621
pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][candidate_count++] =
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
630
pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][candidate_count++] =
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
634
pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index] = candidate_count;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
637
sort(pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
638
pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
640
remove_duplicates(pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
641
&pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
643
pmo->scratch.pmo_dcn3.current_candidate[stream_index] =
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
644
pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index] - 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
660
pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][pmo->scratch.pmo_dcn3.current_candidate[stream_index]] * 1000) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
678
if (pmo->scratch.pmo_dcn3.cur_latency_index < pmo->scratch.pmo_dcn3.max_latency_index) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
680
pmo->scratch.pmo_dcn3.cur_latency_index++;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
688
pmo->scratch.pmo_dcn3.cur_latency_index = pmo->scratch.pmo_dcn3.min_latency_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
697
in_out->optimized_display_config->stage3.min_clk_index_for_latency = pmo->scratch.pmo_dcn3.cur_latency_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
701
pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][pmo->scratch.pmo_dcn3.current_candidate[stream_index]]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1000
valid &= is_bit_set_in_bitfield(pmo->scratch.pmo_dcn4.stream_vactive_capability_mask, i);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1018
if (mask != pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[i]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1049
stream_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[i];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1127
stream_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[i];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1133
microschedule_vlines = calc_svp_microschedule(&pmo->scratch.pmo_dcn4.stream_fams2_meta[i]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1154
static void insert_into_candidate_list(const struct dml2_pmo_pstate_strategy *pstate_strategy, int stream_count, struct dml2_pmo_scratch *scratch)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1156
scratch->pmo_dcn4.pstate_strategy_candidates[scratch->pmo_dcn4.num_pstate_candidates] = *pstate_strategy;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1157
scratch->pmo_dcn4.num_pstate_candidates++;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1260
stream_method_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_idx].method_vactive.common;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1264
stream_method_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_idx].method_vblank.common;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1268
stream_method_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_idx].method_subvp.common;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1271
stream_method_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_idx].method_drr.common;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1297
struct dml2_pmo_scratch *s = &pmo->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1316
if (is_bit_set_in_bitfield(pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], i)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1340
build_method_scheduling_params(group_fams2_meta, &pmo->scratch.pmo_dcn4.stream_fams2_meta[base_stream_idx]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1353
struct dml2_pmo_scratch *s = &pmo->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1570
struct dml2_pmo_scratch *s = &pmo->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1672
struct dml2_fams2_meta *stream_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1822
struct dml2_implicit_svp_meta *stream_svp_meta = &pmo->scratch.pmo_dcn4.stream_svp_meta[stream_index];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1823
struct dml2_fams2_meta *stream_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1837
struct dml2_pmo_scratch *s = &pmo->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1859
pmo->scratch.pmo_dcn4.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1860
pmo->scratch.pmo_dcn4.max_latency_index = pmo->mcg_clock_table_size;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1861
pmo->scratch.pmo_dcn4.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1986
struct dml2_pmo_scratch *scratch = &pmo->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2000
&scratch->pmo_dcn4.stream_svp_meta[stream_index],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2009
struct dml2_pmo_scratch *scratch = &pmo->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2023
&scratch->pmo_dcn4.stream_svp_meta[stream_index],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2080
(unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2101
(unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2109
struct dml2_pmo_scratch *scratch = &pmo->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2119
if (pmo->scratch.pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_na) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2122
} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_vactive) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2123
setup_planes_for_vactive_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2124
} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_vblank) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2125
setup_planes_for_vblank_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2126
} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2128
setup_planes_for_svp_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2129
} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vactive_drr) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2131
setup_planes_for_vactive_drr_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2132
} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vblank_drr) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2134
setup_planes_for_vblank_drr_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2135
} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp_drr) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2137
setup_planes_for_svp_drr_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2138
} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_drr) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2140
setup_planes_for_drr_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2148
&scratch->pmo_dcn4.stream_fams2_meta,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2173
struct dml2_pmo_scratch *s = &in_out->instance->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2232
struct dml2_pmo_scratch *s = &in_out->instance->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2256
setup_display_config(in_out->optimized_display_config, in_out->instance, in_out->instance->scratch.pmo_dcn4.cur_pstate_candidate);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2301
pmo->scratch.pmo_dcn4.num_stutter_candidates = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2302
pmo->scratch.pmo_dcn4.cur_stutter_candidate = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2306
pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.num_stutter_candidates] = (unsigned int)pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2307
pmo->scratch.pmo_dcn4.num_stutter_candidates++;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2308
pmo->scratch.pmo_dcn4.z8_vblank_optimizable = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2311
pmo->scratch.pmo_dcn4.z8_vblank_optimizable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2315
pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.num_stutter_candidates] = (unsigned int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2316
pmo->scratch.pmo_dcn4.num_stutter_candidates++;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2319
if (pmo->scratch.pmo_dcn4.num_stutter_candidates == 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2334
pmo->scratch.pmo_dcn4.z8_vblank_optimizable &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2358
if (pmo->scratch.pmo_dcn4.cur_stutter_candidate < pmo->scratch.pmo_dcn4.num_stutter_candidates) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2362
(long)math_max2(pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.cur_stutter_candidate] * 1000,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
943
struct dml2_pmo_scratch *s = &pmo->scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
980
set_bit_in_bitfield(&pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], j);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
1112
struct dml2_initialize_instance_locals *l = &dml->scratch.initialize_instance_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
511
struct dml2_top_mcache_validate_admissability_locals *l = &dml->scratch.mcache_validate_admissability_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
731
struct dml2_top_mcache_verify_mcache_size_locals *l = &dml->scratch.mcache_verify_mcache_size_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
778
struct dml2_check_mode_supported_locals *l = &dml->scratch.check_mode_supported_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
827
struct dml2_build_mode_programming_locals *l = &dml->scratch.build_mode_programming_locals;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
479
struct dml2_core_scratch scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
734
struct dml2_pmo_scratch scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
980
} scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
985
} scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1048
struct dc_pipe_mapping_scratch scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1076
memset(&scratch, 0, sizeof(struct dc_pipe_mapping_scratch));
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1085
scratch.odm_info.odm_factor = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1087
scratch.odm_info.odm_factor = 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1089
scratch.odm_info.odm_factor = 4;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1092
scratch.odm_info.odm_factor = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1100
scratch.odm_info.odm_factor = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1102
scratch.odm_info.odm_factor = 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1104
scratch.odm_info.odm_factor = 4;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1107
scratch.odm_info.odm_factor = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1110
calculate_odm_slices(state->streams[stream_index], scratch.odm_info.odm_factor, scratch.odm_info.odm_slice_end_x);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1114
map_pipes_for_stream(ctx, state, state->streams[stream_index], &scratch, existing_state);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1124
scratch.mpc_info.prev_odm_pipe = NULL;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1125
if (scratch.odm_info.odm_factor == 1 && plane_disp_cfg_index < disp_cfg_index_max) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1128
scratch.mpc_info.mpc_factor = DPPPerSurface[plane_disp_cfg_index];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1132
scratch.mpc_info.mpc_factor = 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1136
scratch.mpc_info.mpc_factor = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1139
ASSERT(scratch.odm_info.odm_factor * scratch.mpc_info.mpc_factor > 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1142
memset(&scratch.pipe_pool, 0, sizeof(struct dc_plane_pipe_pool));
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1145
state->stream_status[stream_index].plane_states[plane_index], plane_index, &scratch, existing_state);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
132
ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
155
ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[pipe->pipe_idx],
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
535
struct dc_pipe_mapping_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
543
ASSERT(scratch->pipe_pool.num_pipes_assigned_to_plane_for_mpcc_combine == 1 || scratch->pipe_pool.num_pipes_assigned_to_plane_for_odm_combine == 1);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
545
for (i = 0; i < scratch->pipe_pool.num_pipes_assigned_to_plane_for_mpcc_combine; i++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
546
pipe = &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
548
if (scratch->mpc_info.prev_odm_pipe)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
549
scratch->mpc_info.prev_odm_pipe->next_odm_pipe = pipe;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
551
pipe->prev_odm_pipe = scratch->mpc_info.prev_odm_pipe;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
554
scratch->mpc_info.prev_odm_pipe = pipe;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
62
bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
704
bool is_plane_duplicate = ctx->v20.scratch.plane_duplicate_exists;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
710
ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx] == plane_index) &&
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
735
struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
741
master_pipe = assign_pipes_to_stream(ctx, state, stream, scratch->odm_info.odm_factor, &scratch->pipe_pool, existing_state);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
742
sort_pipes_for_splitting(&scratch->pipe_pool);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
744
for (odm_slice_index = 0; odm_slice_index < scratch->odm_info.odm_factor; odm_slice_index++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
745
remove_pipes_from_blend_trees(ctx, state, &scratch->pipe_pool, odm_slice_index);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
747
add_odm_slice_to_odm_tree(ctx, state, scratch, odm_slice_index);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
750
master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][0]], true);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
755
int plane_index, struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
767
master_pipe = assign_pipes_to_plane(ctx, state, stream, plane, scratch->odm_info.odm_factor,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
768
scratch->mpc_info.mpc_factor, plane_index, &scratch->pipe_pool, existing_state);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
769
sort_pipes_for_splitting(&scratch->pipe_pool);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
771
for (odm_slice_index = 0; odm_slice_index < scratch->odm_info.odm_factor; odm_slice_index++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
773
scratch->odm_info.next_higher_pipe_for_odm_slice[odm_slice_index] = add_plane_to_blend_tree(ctx, state,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
775
&scratch->pipe_pool,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
777
scratch->odm_info.next_higher_pipe_for_odm_slice[odm_slice_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
779
add_odm_slice_to_odm_tree(ctx, state, scratch, odm_slice_index);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
781
for (i = 0; i < scratch->pipe_pool.num_pipes_assigned_to_plane_for_mpcc_combine; i++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
784
master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]], true);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
788
free_unused_pipes_for_plane(ctx, state, plane, &scratch->pipe_pool, stream->stream_id, plane_index);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
143
struct dml2_wrapper_scratch scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
147
struct dml21_wrapper_scratch scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1137
if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == stream->stream_id) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1150
bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1183
if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1197
struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1274
dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[i] = -1;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1284
dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_stream_enc->inst] =
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1298
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1299
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1300
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1301
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1350
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context->streams[i]->stream_id;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1351
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1362
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1394
&dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1395
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1416
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_plane_location] = context->streams[i]->stream_id;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1417
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_plane_location] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
330
struct dml2_policy_build_synthetic_soc_states_scratch *s = &dml2->v20.scratch.create_scratch.build_synthetic_socbb_scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
331
struct dml2_policy_build_synthetic_soc_states_params *p = &dml2->v20.scratch.build_synthetic_socbb_params;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
349
p->in_states = &dml2->v20.scratch.create_scratch.in_states;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
793
if (location < MAX_HPO_DP2_ENCODERS && dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
794
out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
198
if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] == stream_id)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
209
if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
220
bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
283
struct dml2_calculate_rq_and_dlg_params_scratch *s = &in_ctx->v20.scratch.calculate_rq_and_dlg_params_scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
307
in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
315
ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[dml_pipe_idx]);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
316
ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
364
context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
366
context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
524
in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id))
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
539
det_scratch->dpps_per_surface[i] = in_ctx->v20.scratch.cur_display_config.hw.DPPPerSurface[i];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
160
struct dml2_calculate_lowest_supported_state_for_temp_read_scratch *s = &dml2->v20.scratch.dml2_calculate_lowest_supported_state_for_temp_read_scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
161
struct dml2_wrapper_scratch *s_global = &dml2->v20.scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
269
struct dml2_wrapper_scratch *s = &dml2->v20.scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
367
struct dml2_wrapper_scratch *s = &dml2->v20.scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
402
struct dml2_wrapper_scratch *s = &dml2->v20.scratch;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
425
memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
519
memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
526
map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
528
dml2_apply_det_buffer_allocation_policy(dml2, &dml2->v20.scratch.cur_display_config);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
531
&dml2->v20.scratch.cur_display_config,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
532
&dml2->v20.scratch.mode_support_info,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
536
result = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.scratch.mode_support_info);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
85
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
86
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
87
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
88
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
99
struct dml2_wrapper_scratch *s = &dml2->v20.scratch;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1732
if (dc->scratch.pipes_to_unlock_first[i]) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1742
if (dc->scratch.pipes_to_unlock_first[i])
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
339
uint32_t scratch[17];
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
124
scratch = dmub->hw_funcs.get_gpint_response(dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
125
if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
433
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
434
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
435
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
436
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
437
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
438
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
439
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
440
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
441
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
442
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
443
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
444
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
445
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
446
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
447
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
448
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
98
uint32_t in_reset, scratch, i;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
111
scratch = REG_READ(DMCUB_SCRATCH7);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
112
if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
434
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
435
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
436
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
437
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
438
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
439
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
440
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
441
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
442
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
443
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
444
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
445
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
446
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
447
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
448
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
449
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
87
uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
113
scratch = REG_READ(DMCUB_SCRATCH7);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
114
if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
442
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
443
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
444
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
445
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
446
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
447
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
448
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
449
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
450
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
451
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
452
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
453
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
454
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
455
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
456
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
457
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
458
dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
93
uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
112
scratch = REG_READ(DMCUB_SCRATCH7);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
113
if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
472
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
473
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
474
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
475
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
476
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
477
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
478
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
479
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
480
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
481
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
482
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
483
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
484
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
485
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
486
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
487
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
488
dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
92
uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
430
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
431
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
432
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
433
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
434
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
435
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
436
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
437
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
438
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
439
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
440
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
441
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
442
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
443
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
444
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
445
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
446
dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
69
uint32_t enabled, in_reset, scratch, pwait_mode;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
84
scratch = dmub->hw_funcs.get_gpint_response(dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
85
if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
731
unsigned long scratch;
sys/dev/pci/drm/i915/gem/selftests/huge_gem_object.c
128
obj->scratch = phys_size;
sys/dev/pci/drm/i915/gem/selftests/huge_gem_object.c
14
unsigned long nreal = obj->scratch / PAGE_SIZE;
sys/dev/pci/drm/i915/gem/selftests/huge_gem_object.c
31
const unsigned long nreal = obj->scratch / PAGE_SIZE;
sys/dev/pci/drm/i915/gem/selftests/huge_gem_object.h
24
return obj->scratch;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
103
struct blit_buffer scratch;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
266
i915_vma_put(t->scratch.vma);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
310
t->scratch.vma = create_vma(t, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
311
if (IS_ERR(t->scratch.vma)) {
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
313
return PTR_ERR(t->scratch.vma);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
337
t->scratch.start_val = val;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
341
i915_gem_object_flush_map(t->scratch.vma->obj);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
606
map = i915_gem_object_pin_map_unlocked(t->scratch.vma->obj, I915_MAP_WC);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
613
GEM_BUG_ON(verify_buffer(t, &t->scratch, prng));
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
617
&t->scratch, t->hole);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
626
i915_gem_object_unpin_map(t->scratch.vma->obj);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1754
if (!vm->scratch[0]) {
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1759
vaddr = __px_vaddr(vm->scratch[0]);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
189
const unsigned int nreal = obj->scratch / PAGE_SIZE;
sys/dev/pci/drm/i915/gt/gen2_engine_cs.c
194
GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
193
fill32_px(pt, vm->scratch[0]->encode);
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
228
vm->scratch[0]->encode =
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
229
vm->pte_encode(px_dma(vm->scratch[0]),
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
23
dma_addr_t addr = pt ? px_dma(pt) : px_dma(ppgtt->base.vm.scratch[1]);
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
234
vm->scratch[1] = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
235
if (IS_ERR(vm->scratch[1])) {
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
236
ret = PTR_ERR(vm->scratch[1]);
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
240
ret = map_pt_dma(vm, vm->scratch[1]);
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
244
fill32_px(vm->scratch[1], vm->scratch[0]->encode);
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
249
i915_gem_object_put(vm->scratch[1]);
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
251
i915_gem_object_put(vm->scratch[0]);
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
252
vm->scratch[0] = NULL;
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
79
const gen6_pte_t scratch_pte = vm->scratch[0]->encode;
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
243
const struct drm_i915_gem_object * const scratch = vm->scratch[lvl];
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
261
clear_pd_entry(pd, idx, scratch);
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
293
vm->scratch[0]->encode,
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
300
if (release_pd_entry(pd, idx, pt, scratch))
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
351
fill_px(pt, vm->scratch[lvl]->encode);
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
721
encode = vm->scratch[0]->encode;
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
843
vm->scratch[i] = i915_gem_object_get(clone->scratch[i]);
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
853
if (i915_gem_object_is_lmem(vm->scratch[0]))
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
856
vm->scratch[0]->encode =
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
857
vm->pte_encode(px_dma(vm->scratch[0]),
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
877
fill_px(obj, vm->scratch[i - 1]->encode);
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
880
vm->scratch[i] = obj;
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
887
i915_gem_object_put(vm->scratch[i]);
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
888
vm->scratch[0] = NULL;
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
915
fill_px(pde, vm->scratch[1]->encode);
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
948
fill_page_dma(px_base(pd), vm->scratch[vm->top]->encode, count);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1318
GEM_BUG_ON(!engine->gt->scratch);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1043
i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1045
i915_gem_object_unlock(ppgtt->vm.scratch[0]);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1266
if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1269
ggtt->vm.scratch[0]->encode =
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1270
ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1336
if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1339
ggtt->vm.scratch[0]->encode =
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1340
ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
sys/dev/pci/drm/i915/gt/intel_ggtt.c
375
const gen8_pte_t scratch_pte = ggtt->vm.scratch[0]->encode;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
542
gen8_set_pte(gte++, vm->scratch[0]->encode);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
551
gen8_set_pte(gte++, vm->scratch[0]->encode);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
565
gen8_pte_t scratch_pte = vm->scratch[0]->encode;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
610
const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
631
const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
694
iowrite32(vm->scratch[0]->encode, gte++);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
702
iowrite32(vm->scratch[0]->encode, gte++);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
801
scratch_pte = vm->scratch[0]->encode;
sys/dev/pci/drm/i915/gt/intel_gt.c
492
gt->scratch = i915_vma_make_unshrinkable(vma);
sys/dev/pci/drm/i915/gt/intel_gt.c
503
i915_vma_unpin_and_release(>->scratch, 0);
sys/dev/pci/drm/i915/gt/intel_gt.h
158
return i915_ggtt_offset(gt->scratch) + field;
sys/dev/pci/drm/i915/gt/intel_gt_types.h
235
struct i915_vma *scratch;
sys/dev/pci/drm/i915/gt/intel_gtt.c
200
if (vm->scratch[0]->base.resv == &vm->_resv) {
sys/dev/pci/drm/i915/gt/intel_gtt.c
201
return i915_gem_object_lock(vm->scratch[0], ww);
sys/dev/pci/drm/i915/gt/intel_gtt.c
346
static void poison_scratch_page(struct drm_i915_gem_object *scratch)
sys/dev/pci/drm/i915/gt/intel_gtt.c
348
void *vaddr = __px_vaddr(scratch);
sys/dev/pci/drm/i915/gt/intel_gtt.c
355
memset(vaddr, val, scratch->base.size);
sys/dev/pci/drm/i915/gt/intel_gtt.c
356
drm_clflush_virt_range(vaddr, scratch->base.size);
sys/dev/pci/drm/i915/gt/intel_gtt.c
409
vm->scratch[0] = obj;
sys/dev/pci/drm/i915/gt/intel_gtt.c
427
if (!vm->scratch[0])
sys/dev/pci/drm/i915/gt/intel_gtt.c
431
i915_gem_object_put(vm->scratch[i]);
sys/dev/pci/drm/i915/gt/intel_gtt.h
274
struct drm_i915_gem_object *scratch[4];
sys/dev/pci/drm/i915/gt/intel_gtt.h
585
return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
sys/dev/pci/drm/i915/gt/intel_gtt.h
662
const struct drm_i915_gem_object * const scratch);
sys/dev/pci/drm/i915/gt/intel_gtt.h
668
const struct drm_i915_gem_object * const scratch);
sys/dev/pci/drm/i915/gt/intel_ppgtt.c
115
const struct drm_i915_gem_object * const scratch)
sys/dev/pci/drm/i915/gt/intel_ppgtt.c
119
write_dma_entry(px_base(pd), idx, scratch->encode);
sys/dev/pci/drm/i915/gt/intel_ppgtt.c
128
const struct drm_i915_gem_object * const scratch)
sys/dev/pci/drm/i915/gt/intel_ppgtt.c
137
clear_pd_entry(pd, idx, scratch);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
4194
struct i915_vma *scratch;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
4200
scratch =
sys/dev/pci/drm/i915/gt/selftest_execlists.c
4203
if (IS_ERR(scratch))
sys/dev/pci/drm/i915/gt/selftest_execlists.c
4204
return PTR_ERR(scratch);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
4206
err = i915_vma_sync(scratch);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
4246
*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
4266
cs = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
4281
i915_gem_object_unpin_map(scratch->obj);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
4292
i915_vma_unpin_and_release(&scratch, 0);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1040
*cs++ = lower_32_bits(i915_vma_offset(scratch) + x);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1041
*cs++ = upper_32_bits(i915_vma_offset(scratch) + x);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
404
struct i915_vma *scratch)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
425
err = i915_gem_object_lock(scratch->obj, &ww);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
446
*cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
453
*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
456
err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
471
cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
486
i915_gem_object_unpin_map(scratch->obj);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
507
struct i915_vma *scratch;
sys/dev/pci/drm/i915/gt/selftest_lrc.c
516
scratch = create_scratch(gt);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
517
if (IS_ERR(scratch))
sys/dev/pci/drm/i915/gt/selftest_lrc.c
518
return PTR_ERR(scratch);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
521
err = __live_lrc_state(engine, scratch);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
529
i915_vma_unpin_and_release(&scratch, 0);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
565
__gpr_read(struct intel_context *ce, struct i915_vma *scratch, u32 *slot)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
599
*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
603
err = igt_vma_move_to_active_unlocked(scratch, rq, EXEC_OBJECT_WRITE);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
616
struct i915_vma *scratch,
sys/dev/pci/drm/i915/gt/selftest_lrc.c
637
rq = __gpr_read(ce, scratch, slot);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
669
cs = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
686
i915_gem_object_unpin_map(scratch->obj);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
701
struct i915_vma *scratch;
sys/dev/pci/drm/i915/gt/selftest_lrc.c
710
scratch = create_scratch(gt);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
711
if (IS_ERR(scratch))
sys/dev/pci/drm/i915/gt/selftest_lrc.c
712
return PTR_ERR(scratch);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
717
err = __live_lrc_gpr(engine, scratch, false);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
721
err = __live_lrc_gpr(engine, scratch, true);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
733
i915_vma_unpin_and_release(&scratch, 0);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
973
store_context(struct intel_context *ce, struct i915_vma *scratch)
sys/dev/pci/drm/i915/gt/selftest_mocs.c
20
struct i915_vma *scratch;
sys/dev/pci/drm/i915/gt/selftest_mocs.c
220
struct i915_vma *vma = arg->scratch;
sys/dev/pci/drm/i915/gt/selftest_mocs.c
79
arg->scratch =
sys/dev/pci/drm/i915/gt/selftest_mocs.c
81
if (IS_ERR(arg->scratch))
sys/dev/pci/drm/i915/gt/selftest_mocs.c
82
return PTR_ERR(arg->scratch);
sys/dev/pci/drm/i915/gt/selftest_mocs.c
84
arg->vaddr = i915_gem_object_pin_map_unlocked(arg->scratch->obj, I915_MAP_WB);
sys/dev/pci/drm/i915/gt/selftest_mocs.c
93
i915_vma_unpin_and_release(&arg->scratch, 0);
sys/dev/pci/drm/i915/gt/selftest_mocs.c
99
i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1061
struct i915_vma *scratch[2];
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1076
client[i].scratch[0] =
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1078
if (IS_ERR(client[i].scratch[0])) {
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1079
err = PTR_ERR(client[i].scratch[0]);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1083
client[i].scratch[1] =
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1085
if (IS_ERR(client[i].scratch[1])) {
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1086
err = PTR_ERR(client[i].scratch[1]);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1087
i915_vma_unpin_and_release(&client[i].scratch[0], 0);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1114
err = read_whitelisted_registers(ce[0], client[0].scratch[0]);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1124
err = read_whitelisted_registers(ce[1], client[1].scratch[0]);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1130
client[0].scratch[0],
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1131
client[1].scratch[0],
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1137
err = read_whitelisted_registers(ce[0], client[0].scratch[1]);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1143
client[0].scratch[0],
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1144
client[0].scratch[1],
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1155
i915_vma_unpin_and_release(&client[i].scratch[1], 0);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1156
i915_vma_unpin_and_release(&client[i].scratch[0], 0);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
503
struct i915_vma *scratch;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
509
scratch = __vm_create_scratch_for_read_pinned(ce->vm, sz);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
510
if (IS_ERR(scratch))
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
511
return PTR_ERR(scratch);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
522
u64 addr = i915_vma_offset(scratch);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
540
err = i915_gem_object_lock(scratch->obj, &ww);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
554
results = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
604
GEM_BUG_ON(idx * sizeof(u32) > scratch->size);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
635
err = i915_vma_move_to_active(scratch, rq,
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
730
i915_gem_object_unpin_map(scratch->obj);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
752
i915_vma_unpin_and_release(&scratch, 0);
sys/dev/pci/drm/i915/i915_perf.c
1383
struct i915_vma *scratch;
sys/dev/pci/drm/i915/i915_perf.c
1387
scratch = __vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);
sys/dev/pci/drm/i915/i915_perf.c
1388
if (IS_ERR(scratch))
sys/dev/pci/drm/i915/i915_perf.c
1389
return PTR_ERR(scratch);
sys/dev/pci/drm/i915/i915_perf.c
1391
err = i915_vma_sync(scratch);
sys/dev/pci/drm/i915/i915_perf.c
1396
i915_ggtt_offset(scratch));
sys/dev/pci/drm/i915/i915_perf.c
1400
val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
sys/dev/pci/drm/i915/i915_perf.c
1407
i915_gem_object_unpin_map(scratch->obj);
sys/dev/pci/drm/i915/i915_perf.c
1410
i915_vma_unpin_and_release(&scratch, 0);
sys/dev/pci/drm/i915/selftests/i915_perf.c
296
void *scratch;
sys/dev/pci/drm/i915/selftests/i915_perf.c
316
scratch = __px_vaddr(ce->vm->scratch[0]);
sys/dev/pci/drm/i915/selftests/i915_perf.c
317
memset(scratch, POISON_FREE, PAGE_SIZE);
sys/dev/pci/drm/i915/selftests/i915_perf.c
405
if (memchr_inv(scratch, POISON_FREE, PAGE_SIZE)) {
sys/dev/pci/drm/i915/selftests/i915_perf.c
407
igt_hexdump(scratch, 4096);
sys/dev/pci/drm/include/uapi/drm/radeon_drm.h
277
} scratch;
sys/dev/pci/drm/radeon/atom.c
1438
ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
sys/dev/pci/drm/radeon/atom.c
1439
if (!ctx->scratch)
sys/dev/pci/drm/radeon/atom.c
295
val = gctx->scratch[(gctx->fb_base / 4) + idx];
sys/dev/pci/drm/radeon/atom.c
558
gctx->scratch[(gctx->fb_base / 4) + idx] = val;
sys/dev/pci/drm/radeon/atom.h
141
uint32_t *scratch;
sys/dev/pci/drm/radeon/atombios_dp.c
103
base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
sys/dev/pci/drm/radeon/atombios_i2c.c
53
base = (unsigned char *)rdev->mode_info.atom_context->scratch;
sys/dev/pci/drm/radeon/cik.c
3426
rdev->scratch.num_reg = 7;
sys/dev/pci/drm/radeon/cik.c
3427
rdev->scratch.reg_base = SCRATCH_REG0;
sys/dev/pci/drm/radeon/cik.c
3428
for (i = 0; i < rdev->scratch.num_reg; i++) {
sys/dev/pci/drm/radeon/cik.c
3429
rdev->scratch.free[i] = true;
sys/dev/pci/drm/radeon/cik.c
3430
rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
sys/dev/pci/drm/radeon/cik.c
3447
uint32_t scratch;
sys/dev/pci/drm/radeon/cik.c
3452
r = radeon_scratch_get(rdev, &scratch);
sys/dev/pci/drm/radeon/cik.c
3457
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/cik.c
3461
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/cik.c
3465
radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
sys/dev/pci/drm/radeon/cik.c
3470
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/cik.c
3479
ring->idx, scratch, tmp);
sys/dev/pci/drm/radeon/cik.c
3482
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/cik.c
3772
uint32_t scratch;
sys/dev/pci/drm/radeon/cik.c
3777
r = radeon_scratch_get(rdev, &scratch);
sys/dev/pci/drm/radeon/cik.c
3782
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/cik.c
3786
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/cik.c
3790
ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
sys/dev/pci/drm/radeon/cik.c
3795
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/cik.c
3804
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/cik.c
3809
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/cik.c
3815
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/cik.c
3824
scratch, tmp);
sys/dev/pci/drm/radeon/cik.c
3827
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/r100.c
3677
uint32_t scratch;
sys/dev/pci/drm/radeon/r100.c
3682
r = radeon_scratch_get(rdev, &scratch);
sys/dev/pci/drm/radeon/r100.c
3687
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/r100.c
3691
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/r100.c
3694
radeon_ring_write(ring, PACKET0(scratch, 0));
sys/dev/pci/drm/radeon/r100.c
3698
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r100.c
3708
scratch, tmp);
sys/dev/pci/drm/radeon/r100.c
3711
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/r100.c
3733
uint32_t scratch;
sys/dev/pci/drm/radeon/r100.c
3738
r = radeon_scratch_get(rdev, &scratch);
sys/dev/pci/drm/radeon/r100.c
3743
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/r100.c
3749
ib.ptr[0] = PACKET0(scratch, 0);
sys/dev/pci/drm/radeon/r100.c
3775
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r100.c
3785
scratch, tmp);
sys/dev/pci/drm/radeon/r100.c
3791
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/r600.c
2815
rdev->scratch.num_reg = 7;
sys/dev/pci/drm/radeon/r600.c
2816
rdev->scratch.reg_base = SCRATCH_REG0;
sys/dev/pci/drm/radeon/r600.c
2817
for (i = 0; i < rdev->scratch.num_reg; i++) {
sys/dev/pci/drm/radeon/r600.c
2818
rdev->scratch.free[i] = true;
sys/dev/pci/drm/radeon/r600.c
2819
rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
sys/dev/pci/drm/radeon/r600.c
2825
uint32_t scratch;
sys/dev/pci/drm/radeon/r600.c
2830
r = radeon_scratch_get(rdev, &scratch);
sys/dev/pci/drm/radeon/r600.c
2835
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/r600.c
2839
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/r600.c
2843
radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
sys/dev/pci/drm/radeon/r600.c
2847
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r600.c
2856
ring->idx, scratch, tmp);
sys/dev/pci/drm/radeon/r600.c
2859
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/r600.c
3399
uint32_t scratch;
sys/dev/pci/drm/radeon/r600.c
3404
r = radeon_scratch_get(rdev, &scratch);
sys/dev/pci/drm/radeon/r600.c
3409
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/r600.c
3416
ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
sys/dev/pci/drm/radeon/r600.c
3436
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r600.c
3445
scratch, tmp);
sys/dev/pci/drm/radeon/r600.c
3451
radeon_scratch_free(rdev, scratch);
sys/dev/pci/drm/radeon/radeon.h
2407
struct radeon_scratch scratch;
sys/dev/pci/drm/radeon/radeon_device.c
1034
kfree(rdev->mode_info.atom_context->scratch);
sys/dev/pci/drm/radeon/radeon_device.c
273
rdev->scratch.num_reg = 5;
sys/dev/pci/drm/radeon/radeon_device.c
275
rdev->scratch.num_reg = 7;
sys/dev/pci/drm/radeon/radeon_device.c
277
rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
sys/dev/pci/drm/radeon/radeon_device.c
278
for (i = 0; i < rdev->scratch.num_reg; i++) {
sys/dev/pci/drm/radeon/radeon_device.c
279
rdev->scratch.free[i] = true;
sys/dev/pci/drm/radeon/radeon_device.c
280
rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
sys/dev/pci/drm/radeon/radeon_device.c
297
for (i = 0; i < rdev->scratch.num_reg; i++) {
sys/dev/pci/drm/radeon/radeon_device.c
298
if (rdev->scratch.free[i]) {
sys/dev/pci/drm/radeon/radeon_device.c
299
rdev->scratch.free[i] = false;
sys/dev/pci/drm/radeon/radeon_device.c
300
*reg = rdev->scratch.reg[i];
sys/dev/pci/drm/radeon/radeon_device.c
319
for (i = 0; i < rdev->scratch.num_reg; i++) {
sys/dev/pci/drm/radeon/radeon_device.c
320
if (rdev->scratch.reg[i] == reg) {
sys/dev/pci/drm/radeon/radeon_device.c
321
rdev->scratch.free[i] = true;
sys/dev/pci/drm/radeon/radeon_fence.c
788
rdev->scratch.reg_base;
sys/dev/pci/drm/radeon/si.c
3342
rdev->scratch.num_reg = 7;
sys/dev/pci/drm/radeon/si.c
3343
rdev->scratch.reg_base = SCRATCH_REG0;
sys/dev/pci/drm/radeon/si.c
3344
for (i = 0; i < rdev->scratch.num_reg; i++) {
sys/dev/pci/drm/radeon/si.c
3345
rdev->scratch.free[i] = true;
sys/dev/pci/drm/radeon/si.c
3346
rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
sys/dev/pci/if_iwm.c
1471
+ offsetof(struct iwm_tx_cmd, scratch);
sys/dev/pci/if_iwmreg.h
4921
} scratch; /* DRAM_SCRATCH_API_U_VER_1 */
sys/dev/pci/if_iwn.c
3442
tx->scratch = 0; /* clear "scratch" area */
sys/dev/pci/if_iwnreg.h
708
uint32_t scratch;
sys/kern/subr_evcount.c
104
uint64_t count, scratch;
sys/kern/subr_evcount.c
132
counters_read(ec->ec_percpu, &count, 1, &scratch);
sys/kern/subr_percpu.c
163
uint64_t *scratch)
sys/kern/subr_percpu.c
166
uint64_t *gen, *counters, *temp = scratch;
sys/kern/subr_percpu.c
173
if (scratch == NULL)
sys/kern/subr_percpu.c
207
if (scratch == NULL)
sys/kern/subr_percpu.c
312
uint64_t *scratch)
sys/net/pf.c
9150
uint64_t scratch[FCNT_MAX];
sys/net/pf.c
9161
counters_read(pf_status_fcounters, pfs->fcounters, FCNT_MAX, scratch);
sys/uvm/uvm_meter.c
255
uint64_t counters[exp_ncounters], scratch[exp_ncounters];
sys/uvm/uvm_meter.c
259
counters_read(uvmexp_counters, counters, exp_ncounters, scratch);
usr.bin/dig/lib/dns/message.c
757
isc_buffer_t *scratch;
usr.bin/dig/lib/dns/message.c
761
scratch = currentbuffer(msg);
usr.bin/dig/lib/dns/message.c
770
scratch);
usr.bin/dig/lib/dns/message.c
779
scratch = currentbuffer(msg);
usr.bin/dig/lib/dns/message.c
795
isc_buffer_t *scratch;
usr.bin/dig/lib/dns/message.c
800
scratch = currentbuffer(msg);
usr.bin/dig/lib/dns/message.c
817
scratch);
usr.bin/dig/lib/dns/message.c
836
scratch = currentbuffer(msg);
usr.bin/units/units.c
285
char *scratch, *savescr;
usr.bin/units/units.c
290
savescr = scratch = dupstr(toadd);
usr.bin/units/units.c
291
for (slash = scratch + 1; *slash; slash++)
usr.bin/units/units.c
296
slash = strchr(scratch, '/');
usr.bin/units/units.c
301
item = strtok(scratch, " *\t\n/");
usr.bin/units/units.c
362
scratch = slash + 1;
usr.sbin/lldp/lldp.c
1090
fprintf(scratch, "[|org]");
usr.sbin/lldp/lldp.c
1098
fprintf(scratch, "Org %02X-%02X-%02X subtype %u: ",
usr.sbin/lldp/lldp.c
1101
fprintf(scratch, "%s: ", tlv->name);
usr.sbin/lldp/lldp.c
161
static FILE *scratch;
usr.sbin/lldp/lldp.c
192
scratch = fmemopen(scratch_mem, sizeof(scratch_mem), "w");
usr.sbin/lldp/lldp.c
193
if (scratch == NULL)
usr.sbin/lldp/lldp.c
374
fprintf(scratch, "-");
usr.sbin/lldp/lldp.c
385
fprintf(scratch, "-");
usr.sbin/lldp/lldp.c
396
fprintf(scratch, "-");
usr.sbin/lldp/lldp.c
466
if (fseeko(scratch, 0, SEEK_SET) == -1)
usr.sbin/lldp/lldp.c
473
off_t len = ftello(scratch);
usr.sbin/lldp/lldp.c
509
fprintf(scratch, "%lld%c", d, ival->p);
usr.sbin/lldp/lldp.c
522
fprintf(scratch, "%02x", buf[i]);
usr.sbin/lldp/lldp.c
534
fprintf(scratch, "%s", dst);
usr.sbin/lldp/lldp.c
551
fprintf(scratch, "\n\t");
usr.sbin/lldp/lldp.c
555
fprintf(scratch, "%s", dst);
usr.sbin/lldp/lldp.c
572
fprintf(scratch, "%s", ether_ntoa(ea));
usr.sbin/lldp/lldp.c
601
fprintf(scratch, "reserved (subtype %u) ", subtype);
usr.sbin/lldp/lldp.c
633
fprintf(scratch, "reserved (subtype %u) ", subtype);
usr.sbin/lldp/lldp.c
692
fprintf(scratch, "[|system cap]");
usr.sbin/lldp/lldp.c
710
fprintf(scratch, "%s", sep);
usr.sbin/lldp/lldp.c
713
fprintf(scratch, "Bit%u", i + 1);
usr.sbin/lldp/lldp.c
715
fprintf(scratch, "%s", name);
usr.sbin/lldp/lldp.c
717
fprintf(scratch, ": %s",
usr.sbin/lldp/lldp.c
735
fprintf(scratch, "too short (%zu bytes)", len);
usr.sbin/lldp/lldp.c
743
fprintf(scratch, "address len %zu is longer than tlv", alen);
usr.sbin/lldp/lldp.c
751
fprintf(scratch, "address len %zu is too short", alen);
usr.sbin/lldp/lldp.c
761
fprintf(scratch, "IPv4? ");
usr.sbin/lldp/lldp.c
765
fprintf(scratch, "%s", ipbuf);
usr.sbin/lldp/lldp.c
769
fprintf(scratch, "IPv7? ");
usr.sbin/lldp/lldp.c
773
fprintf(scratch, "%s", ipbuf);
usr.sbin/lldp/lldp.c
778
fprintf(scratch, "802? ");
usr.sbin/lldp/lldp.c
781
fprintf(scratch, "%s", ether_ntoa((struct ether_addr *)abuf));
usr.sbin/lldp/lldp.c
785
fprintf(scratch, "af %u ", aftype);
usr.sbin/lldp/lldp.c
792
fprintf(scratch, ", [|interface number]");
usr.sbin/lldp/lldp.c
801
fprintf(scratch, ", ifIndex %u", ifnum);
usr.sbin/lldp/lldp.c
804
fprintf(scratch, ", port %u", ifnum);
usr.sbin/lldp/lldp.c
807
fprintf(scratch, ", if type %u num %u", buf[0], ifnum);
usr.sbin/lldp/lldp.c
815
fprintf(scratch, ", [|object identifier]");
usr.sbin/lldp/lldp.c
825
fprintf(scratch, ", oid %zu is longer than tlv", alen);
usr.sbin/lldp/lldp.c
828
fprintf(scratch, ", oid ");
usr.sbin/lldp/lldp.c
838
fprintf(scratch, "too short (%zu bytes)", len);
usr.sbin/lldp/lldp.c
844
fprintf(scratch, "-");
usr.sbin/lldp/lldp.c
846
fprintf(scratch, "%u", pvid);
usr.sbin/lldp/lldp.c
869
fprintf(scratch, "too short (%zu bytes)", len);
usr.sbin/lldp/lldp.c
874
fprintf(scratch, "Capability: %s",
usr.sbin/lldp/lldp.c
879
fprintf(scratch, ", Status: %s",
usr.sbin/lldp/lldp.c
886
fprintf(scratch, ", Aggregation Port");
usr.sbin/lldp/lldp.c
889
fprintf(scratch, ", Aggregator");
usr.sbin/lldp/lldp.c
892
fprintf(scratch, ", Aggregator with 1 Aggregation Port");
usr.sbin/lldp/lldp.c
903
fprintf(scratch, ", portid too short (%zu bytes)", len);
usr.sbin/lldp/lldp.c
908
fprintf(scratch, ", Port ID: %u", portid);
usr.sbin/lldp/lldp.c
922
fprintf(scratch, "too short (%zu bytes)", len);
usr.sbin/lldp/lldp.c
928
fprintf(scratch, "Auto-negotiation: %s, ",
usr.sbin/lldp/lldp.c
936
fprintf(scratch, "autoneg too short (%zu bytes)", len);
usr.sbin/lldp/lldp.c
948
fprintf(scratch, "MAUAutoNegCap: 0x%04x, ", autoneg);
usr.sbin/lldp/lldp.c
953
fprintf(scratch, ", mautype too short (%zu bytes)", len);
usr.sbin/lldp/lldp.c
962
fprintf(scratch, "MAU type: %u", mautype);
usr.sbin/lldp/lldp.c
971
fprintf(scratch, "too short (%zu bytes)", len);
usr.sbin/lldp/lldp.c
976
fprintf(scratch, "%u", u16);
usr.sbin/lldp/lldp.c
986
fprintf(scratch, "too short (%zu bytes)", len);
usr.sbin/lldp/lldp.c
991
fprintf(scratch, "Supported: %s",
usr.sbin/lldp/lldp.c
993
fprintf(scratch, ", ALT-B Detection required: %s",
usr.sbin/lldp/lldp.c
995
fprintf(scratch, ", PD Request Spare Pair POE: %s",
usr.sbin/lldp/lldp.c
997
fprintf(scratch, ", PSE Spare Pair POE: %s",
usr.sbin/unbound/cachedb/cachedb.c
411
edns_opt_list_append_ede(&edns.opt_list_out, qstate->env->scratch,
usr.sbin/unbound/cachedb/cachedb.c
421
buf, 0, 1, qstate->env->scratch, 65535, &edns, 1, 0))
usr.sbin/unbound/cachedb/cachedb.c
560
regional_free_all(qstate->env->scratch);
usr.sbin/unbound/cachedb/cachedb.c
561
prs = (struct msg_parse*)regional_alloc(qstate->env->scratch,
usr.sbin/unbound/cachedb/cachedb.c
568
if(parse_packet(buf, prs, qstate->env->scratch) != LDNS_RCODE_NOERROR) {
usr.sbin/unbound/cachedb/cachedb.c
572
if(parse_extract_edns_from_response_msg(prs, &edns, qstate->env->scratch) !=
usr.sbin/unbound/cachedb/cachedb.c
711
qstate->region, qstate->env->scratch,
usr.sbin/unbound/daemon/worker.c
2404
worker->env.scratch = regional_create_custom(cfg->msg_buffer_size);
usr.sbin/unbound/daemon/worker.c
2405
if(!worker->env.scratch) {
usr.sbin/unbound/daemon/worker.c
2527
regional_destroy(worker->env.scratch);
usr.sbin/unbound/edns-subnet/subnetmod.c
574
env->scratch);
usr.sbin/unbound/iterator/iter_utils.c
1260
neg = (struct ub_packed_rrset_key*)regional_alloc(env->scratch,
usr.sbin/unbound/iterator/iter_utils.c
1271
neg->rk.dname = regional_alloc_init(env->scratch, qinfo->qname,
usr.sbin/unbound/iterator/iter_utils.c
1279
newd = (struct packed_rrset_data*)regional_alloc_zero(env->scratch,
usr.sbin/unbound/iterator/iter_utils.c
963
dp->name, dp->namelen, dclass, env->scratch, *env->now);
usr.sbin/unbound/iterator/iter_utils.c
967
regional_free_all(env->scratch);
usr.sbin/unbound/iterator/iter_utils.c
970
regional_free_all(env->scratch);
usr.sbin/unbound/iterator/iter_utils.c
974
regional_free_all(env->scratch);
usr.sbin/unbound/iterator/iterator.c
1524
qstate->region, qstate->env->scratch, 0, dpname,
usr.sbin/unbound/iterator/iterator.c
2683
qstate->env->scratch, 0, iq->dp->name,
usr.sbin/unbound/iterator/iterator.c
4354
prs = (struct msg_parse*)regional_alloc(qstate->env->scratch,
usr.sbin/unbound/iterator/iterator.c
4365
if(parse_packet(pkt, prs, qstate->env->scratch) != LDNS_RCODE_NOERROR) {
usr.sbin/unbound/iterator/iterator.c
4371
if(parse_extract_edns_from_response_msg(prs, &edns, qstate->env->scratch) !=
usr.sbin/unbound/iterator/iterator.c
4398
qstate->env->scratch, qstate->env, qstate, ie)) {
usr.sbin/unbound/iterator/iterator.c
4480
qstate->env->scratch)) {
usr.sbin/unbound/libunbound/libworker.c
100
regional_destroy(w->env->scratch);
usr.sbin/unbound/libunbound/libworker.c
157
w->env->scratch = regional_create_custom(cfg->msg_buffer_size);
usr.sbin/unbound/libunbound/libworker.c
171
if(!w->env->scratch || !w->env->scratch_buffer) {
usr.sbin/unbound/libunbound/libworker.c
571
libworker_enter_result(q->res, buf, q->w->env->scratch, s);
usr.sbin/unbound/libunbound/libworker.c
633
w->back->udp_buff, w->env->scratch, NULL, NULL, 0, NULL, 0,
usr.sbin/unbound/libunbound/libworker.c
635
regional_free_all(w->env->scratch);
usr.sbin/unbound/libunbound/libworker.c
644
w->back->udp_buff, w->env->scratch)) {
usr.sbin/unbound/libunbound/libworker.c
645
regional_free_all(w->env->scratch);
usr.sbin/unbound/libunbound/libworker.c
714
w->back->udp_buff, w->env->scratch, NULL, NULL, 0, NULL, 0,
usr.sbin/unbound/libunbound/libworker.c
716
regional_free_all(w->env->scratch);
usr.sbin/unbound/libunbound/libworker.c
724
w->back->udp_buff, w->env->scratch)) {
usr.sbin/unbound/libunbound/libworker.c
725
regional_free_all(w->env->scratch);
usr.sbin/unbound/libunbound/libworker.c
853
w->back->udp_buff, w->env->scratch, NULL, NULL, 0, NULL, 0,
usr.sbin/unbound/libunbound/libworker.c
855
regional_free_all(w->env->scratch);
usr.sbin/unbound/libunbound/libworker.c
863
w->back->udp_buff, w->env->scratch)) {
usr.sbin/unbound/libunbound/libworker.c
864
regional_free_all(w->env->scratch);
usr.sbin/unbound/services/authzone.c
1774
env.scratch = regional_create();
usr.sbin/unbound/services/authzone.c
1779
if(!env.scratch) {
usr.sbin/unbound/services/authzone.c
1788
regional_destroy(env.scratch);
usr.sbin/unbound/services/authzone.c
1895
region = env->scratch;
usr.sbin/unbound/services/authzone.c
5772
struct regional* temp = env->scratch;
usr.sbin/unbound/services/authzone.c
6865
struct regional* temp = env->scratch;
usr.sbin/unbound/services/authzone.c
8286
regional_free_all(env->scratch);
usr.sbin/unbound/services/authzone.c
8346
regional_free_all(env->scratch);
usr.sbin/unbound/services/authzone.c
8403
struct regional* temp = env->scratch;
usr.sbin/unbound/services/authzone.c
8492
regional_free_all(env->scratch);
usr.sbin/unbound/services/authzone.c
8498
regional_free_all(env->scratch);
usr.sbin/unbound/services/authzone.c
8639
regional_free_all(env->scratch);
usr.sbin/unbound/services/authzone.c
8645
regional_free_all(env->scratch);
usr.sbin/unbound/services/cache/dns.c
1088
&& (msg=tomsg(env, &k, data, region, now, 0, scratch))) {
usr.sbin/unbound/services/cache/dns.c
634
struct regional* scratch)
usr.sbin/unbound/services/cache/dns.c
706
rrset_array_unlock_touch(env->rrset_cache, scratch, r->ref,
usr.sbin/unbound/services/cache/dns.c
946
uint16_t flags, struct regional* region, struct regional* scratch,
usr.sbin/unbound/services/cache/dns.c
967
scratch);
usr.sbin/unbound/services/cache/dns.h
168
int allow_expired, struct regional* scratch);
usr.sbin/unbound/services/cache/dns.h
199
uint16_t flags, struct regional* region, struct regional* scratch,
usr.sbin/unbound/services/cache/rrset.c
405
rrset_array_unlock_touch(struct rrset_cache* r, struct regional* scratch,
usr.sbin/unbound/services/cache/rrset.c
411
scratch, sizeof(hashvalue_type)*count))) {
usr.sbin/unbound/services/cache/rrset.h
206
void rrset_array_unlock_touch(struct rrset_cache* r, struct regional* scratch,
usr.sbin/unbound/services/mesh.c
1389
m->s.env->scratch, udp_size, &r->edns,
usr.sbin/unbound/services/mesh.c
1580
r->qflags, r_buffer, 0, 1, m->s.env->scratch,
usr.sbin/unbound/services/mesh.c
2091
struct regional* region = mstate->s.env->scratch;
usr.sbin/unbound/services/mesh.c
2209
mstate->s.env->scratch);
usr.sbin/unbound/services/mesh.c
2248
regional_free_all(mstate->s.env->scratch);
usr.sbin/unbound/services/mesh.c
356
qstate->env->cfg->serve_expired, qstate->env->scratch);
usr.sbin/unbound/services/mesh.c
450
mesh->env->scratch, LDNS_EDE_OTHER,
usr.sbin/unbound/services/mesh.c
453
LDNS_RCODE_SERVFAIL, edns, rep, mesh->env->scratch, mesh->env->now_tv))
usr.sbin/unbound/services/mesh.c
457
regional_free_all(mesh->env->scratch);
usr.sbin/unbound/services/mesh.c
502
LDNS_RCODE_SERVFAIL, edns, rep, mesh->env->scratch, mesh->env->now_tv))
usr.sbin/unbound/services/mesh.c
521
NULL, LDNS_RCODE_SERVFAIL, edns, rep, mesh->env->scratch, mesh->env->now_tv))
usr.sbin/unbound/services/mesh.c
608
NULL, LDNS_RCODE_SERVFAIL, edns, rep, mesh->env->scratch, mesh->env->now_tv))
usr.sbin/unbound/smallapp/unbound-checkconf.c
138
env.scratch = regional_create();
usr.sbin/unbound/smallapp/unbound-checkconf.c
140
if(!env.scratch || !env.scratch_buffer)
usr.sbin/unbound/smallapp/unbound-checkconf.c
152
regional_destroy(env.scratch);
usr.sbin/unbound/testcode/unitverify.c
320
env.scratch = region;
usr.sbin/unbound/testcode/unitverify.c
362
env.scratch = region;
usr.sbin/unbound/testcode/unitzonemd.c
265
env.scratch = regional_create();
usr.sbin/unbound/testcode/unitzonemd.c
266
if(!env.scratch)
usr.sbin/unbound/testcode/unitzonemd.c
343
regional_destroy(env.scratch);
usr.sbin/unbound/util/module.h
488
struct regional* scratch;
usr.sbin/unbound/validator/autotrust.c
2381
qinfo.qname = regional_alloc_init(env->scratch, tp->name, tp->namelen);
usr.sbin/unbound/validator/autotrust.c
2474
regional_free_all(env->scratch);
usr.sbin/unbound/validator/val_sigcrypt.c
346
digest = regional_alloc(env->scratch, digestlen);
usr.sbin/unbound/validator/val_sigcrypt.c
589
sec = dnskey_verify_rrset_sig(env->scratch,
usr.sbin/unbound/validator/val_sigcrypt.c
735
sec = dnskey_verify_rrset_sig(env->scratch,
usr.sbin/unbound/validator/val_utils.c
436
regional_free_all(env->scratch);
usr.sbin/vmd/vioqcow2.c
595
char *scratch;
usr.sbin/vmd/vioqcow2.c
598
scratch = malloc(disk->clustersz);
usr.sbin/vmd/vioqcow2.c
599
if (!scratch)
usr.sbin/vmd/vioqcow2.c
603
n = pread(base->fd, scratch, disk->clustersz, src);
usr.sbin/vmd/vioqcow2.c
608
n = pwrite(disk->fd, scratch, disk->clustersz, dst);
usr.sbin/vmd/vioqcow2.c
613
free(scratch);
