sys/dev/ic/ac97.h

68

void (*set_clock)(struct ac97_codec_if *codec_if,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5500

if (dc->hwss.set_clock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5501

return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_init.c

78

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_init.c

82

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_init.c

77

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_init.c

82

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_init.c

84

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_init.c

84

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

87

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

89

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

85

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

90

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

89

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

64

.set_clock = dcn10_set_clock,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

341

enum dc_status (*set_clock)(struct dc *dc,

sys/dev/pci/drm/i915/display/intel_gmbus.c

353

set_clock(bus, 1);

sys/dev/pci/drm/i915/display/intel_gmbus.c

365

set_clock(bus, 1);

sys/dev/pci/drm/i915/display/intel_gmbus.c

399

set_clock(cookie, bits & INTEL_BB_SCL);

sys/dev/pci/drm/i915/display/intel_gmbus.c

479

algo->setscl = set_clock;

sys/dev/pci/drm/radeon/radeon_i2c.c

1057

i2c->bit.setscl = set_clock;

sys/dev/pci/drm/radeon/radeon_i2c.c

259

set_clock(cookie, bits & RADEON_BB_SCL);