s32
s32 i;
s32 primary_planes;
s32 y, s32 width, s32 height,
u16 v, s32 t, u32 ileakage, u32 *leakage)
s32 t,
s32 t;
s32 t_slope;
s32 t_intercept;
s32 leakage_minimum_temperature;
s32 leakage_minimum_temperature;
s32 __user *out_fence_ptr;
s32 __user *fence_ptr;
s32 __user *fence_ptr;
struct drm_crtc *crtc, s32 __user *fence_ptr)
static s32 __user *get_out_fence_for_crtc(struct drm_atomic_state *state,
s32 __user *fence_ptr;
s32 __user *fence_ptr)
static s32 __user *get_out_fence_for_connector(struct drm_atomic_state *state,
s32 __user *fence_ptr;
s32 __user *fence_ptr = u64_to_user_ptr(val);
s32 __user *fence_ptr = u64_to_user_ptr(val);
s32 tval_sec;
s32 tval_usec;
return near + (s32) (narrow - near);
static void st_runtime_underflow(struct intel_context_stats *stats, s32 dt)
s32 dt;
return (s32)(cur - ALIGN(seqno, 2)) > 0;
return (s32)(end - start) > 0;
s32 available;
s32 bytes; /* Size in bytes */
s32 units; /* GuC API units - 1MB or 4KB */
s32 count; /* Number of API units */
s32 param;
return (s32)(seq1 - seq2) >= 0;
return (s32)(a - b) >= 0;
s32 prev;
if (is_watertight && (prev + 1) != (s32)ranges->start) {
if (prev >= (s32)ranges->start) {
s32 prev;
if (prev >= (s32)range->start) {
s32 __user *out_fence_ptr;
s32 __user *out_fence_ptr;
s32 adjust_percent;
s32 target_tdp;
(s32)cac_tdp_table->configurable_tdp) / 100;
s32 temperature_low;
s32 temperature_high;
s32 temperature_shutdown;
s32 t;
u16 v, s32 t,
s32 t,
s32 t_slope;
s32 t_intercept;
s32 leakage_minimum_temperature;
s32 priority;
static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
s32 priority = 0;
priority = (s32)p->chunks[i].kdata[2];
u16 v, s32 t, u32 ileakage, u32 *leakage)
s32 t,
s32 t;
s32 leakage_minimum_temperature;
entity->priority = max_t(s32, (s32) sched_list[0]->num_rqs - 1,
(s32) DRM_SCHED_PRIORITY_KERNEL);
sieve_large(uint32_t s32)
uint64_t r, u, s = s32;
debug3("sieve_large %u", s32);
r = BN_mod_word(largebase, s32);