sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

250

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

314

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

364

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

472

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

532

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

562

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

660

uint32_t D2VGA_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

833

HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

861

REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

870

REG_WRITE(D2VGA_CONTROL, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

385

REG_WRITE(D2VGA_CONTROL, 0);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

725

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

734

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

724

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

719

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

578

SR(D2VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

574

SR(D2VGA_CONTROL), \