sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

544

if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

535

if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

802

if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

971

if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1079

if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1350

if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1829

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1830

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1832

value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1833

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

418

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

419

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

421

value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

422

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

249

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

313

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

363

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

471

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

531

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

561

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

659

uint32_t D1VGA_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

832

HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

860

REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

869

REG_WRITE(D1VGA_CONTROL, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

384

REG_WRITE(D1VGA_CONTROL, 0);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

724

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

733

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

723

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

718

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

577

SR(D1VGA_CONTROL), \

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

573

SR(D1VGA_CONTROL), \