rtwn_pci_write_4
rtwn_pci_write_4(sc, R92C_HIMR, 0x00000000);
rtwn_pci_write_4(sc, R88E_HIMR, 0x00000000);
rtwn_pci_write_4(sc, R92C_HIMR, 0x00000000);
rtwn_pci_write_4(sc, R92C_APS_FSMCO,
rtwn_pci_write_4(sc, R92C_APS_FSMCO,
rtwn_pci_write_4(sc, R88E_HIMR, 0);
rtwn_pci_write_4(sc, R88E_HIMRE, 0);
rtwn_pci_write_4(sc, R88E_HISR, status);
rtwn_pci_write_4(sc, R88E_HISRE, estatus);
rtwn_pci_write_4(sc, R88E_HIMR, RTWN_88E_INT_ENABLE);
rtwn_pci_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW);
rtwn_pci_write_4(sc, R92C_HIMR, 0x00000000);
rtwn_pci_write_4(sc, R92C_HISR, status);
rtwn_pci_write_4(sc, R92C_HIMR, RTWN_92C_INT_ENABLE);
rtwn_pci_write_4(sc, R92C_LLT_INIT,
rtwn_pci_write_4(sc, R92C_APS_FSMCO, reg);
rtwn_pci_write_4(sc, R92C_AFE_XTAL_CTRL,
rtwn_pci_write_4(sc, R92C_AFE_XTAL_CTRL, reg);
rtwn_pci_write_4(sc, R92C_INT_MIG, 0);
rtwn_pci_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg);
rtwn_pci_write_4(sc, R92C_APS_FSMCO, rtwn_pci_read_4(sc, R92C_APS_FSMCO) |
rtwn_pci_write_4(sc, R92C_RQPN,
rtwn_pci_write_4(sc, R92C_TCR, tcr);
rtwn_pci_write_4(sc, R92C_BKQ_DESA,
rtwn_pci_write_4(sc, R92C_BEQ_DESA,
rtwn_pci_write_4(sc, R92C_VIQ_DESA,
rtwn_pci_write_4(sc, R92C_VOQ_DESA,
rtwn_pci_write_4(sc, R92C_BCNQ_DESA,
rtwn_pci_write_4(sc, R92C_MGQ_DESA,
rtwn_pci_write_4(sc, R92C_HQ_DESA,
rtwn_pci_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr);
rtwn_pci_write_4(sc, R92C_MCUFWDL, reg);
rtwn_pci_write_4(sc, R92C_LEDCFG0,
void rtwn_pci_write_4(void *, uint16_t, uint32_t);
#define rtwn_bb_write rtwn_pci_write_4
sc->sc_sc.sc_ops.write_4 = rtwn_pci_write_4;