rtwn_bb_write
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
rtwn_bb_write(sc, R92C_FPGA0_RFMOD,
rtwn_bb_write(sc, R92C_FPGA1_RFMOD,
rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
rtwn_bb_write(sc, 0x818, reg);
rtwn_bb_write(sc, R92C_FPGA0_RFMOD,
rtwn_bb_write(sc, R92C_FPGA1_RFMOD,
rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
rtwn_bb_write(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT, reg);
rtwn_bb_write(sc,
rtwn_bb_write(sc, R92C_OFDM0_RXAFE,
rtwn_bb_write(sc, R88F_RX_DFIR,
rtwn_bb_write(sc, R88F_RX_DFIR, reg);
rtwn_bb_write(sc, R92C_TX_IQK_TONE_A, iqk_tone[0]);
rtwn_bb_write(sc, R92C_RX_IQK_TONE_B, iqk_tone[1]);
rtwn_bb_write(sc, R92C_TX_IQK_PI_A, iqk_tone[2]);
rtwn_bb_write(sc, R92C_RX_IQK_PI_A, iqk_tone[3]);
rtwn_bb_write(sc, R92C_TX_IQK_TONE_B, iqk_tone[4]);
rtwn_bb_write(sc, R92C_RX_IQK_TONE_B, iqk_tone[4]);
rtwn_bb_write(sc, R92C_TX_IQK_PI_B, 0x82140102);
rtwn_bb_write(sc, R92C_RX_IQK_PI_B, 0x28160202);
rtwn_bb_write(sc, R92C_RX_IQK_PI_A, 0x28160502);
rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x00462911);
rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0x00000002);
rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0x00000000);
rtwn_bb_write(sc, reg_adda[0], adda_vals[0]);
rtwn_bb_write(sc, reg_adda[i], adda_vals[1]);
rtwn_bb_write(sc, reg_adda[i], adda_vals[2]);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600);
rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22208200);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0),
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), rtwn_bb_read(sc,
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), rtwn_bb_read(sc,
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000);
rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 0x00080000);
rtwn_bb_write(sc, R92C_CONFIG_ANT_B, 0x00080000);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 0x00080000);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x00);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
rtwn_bb_write(sc, reg_adda[i], adda_vals[3]);
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x00);
rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3);
rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3);
rtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
rtwn_bb_write(sc, reg_adda[i], iq_cal_regs->adda[i]);
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA,
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0),
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1),
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0),
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1),
rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR,
rtwn_bb_write(sc, R92C_CONFIG_ANT_A,
rtwn_bb_write(sc, R92C_CONFIG_ANT_B,
rtwn_bb_write(sc, R92C_CCK0_AFESETTING,
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | 0x50);
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | xa_agc);
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | 0x50);
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | xb_agc);
rtwn_bb_write(sc, R92C_TX_IQK_TONE_A, 0x01008c00);
rtwn_bb_write(sc, R92C_RX_IQK_TONE_A, 0x01008c00);
rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg);
rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg);
rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg);
rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg);
rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg);
rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg);
rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg);
rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg);
rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg);
rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
rtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
rtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
rtwn_bb_write(sc, 0xe74, reg);
rtwn_bb_write(sc, 0xe78, reg);
rtwn_bb_write(sc, 0xe7c, reg);
rtwn_bb_write(sc, 0xe80, reg);
rtwn_bb_write(sc, 0xe88, reg);
rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,