sys/dev/ic/rtwn.c

1118

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));

sys/dev/ic/rtwn.c

1123

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));

sys/dev/ic/rtwn.c

1144

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));

sys/dev/ic/rtwn.c

1149

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));

sys/dev/ic/rtwn.c

1899

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));

sys/dev/ic/rtwn.c

1903

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));

sys/dev/ic/rtwn.c

1908

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));

sys/dev/ic/rtwn.c

1913

reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));

sys/dev/ic/rtwn.c

1917

reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));

sys/dev/ic/rtwn.c

1951

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));

sys/dev/ic/rtwn.c

2091

reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);

sys/dev/ic/rtwn.c

2094

reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/dev/ic/rtwn.c

2100

reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);

sys/dev/ic/rtwn.c

2105

reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/dev/ic/rtwn.c

2442

rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);

sys/dev/ic/rtwn.c

2444

rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);

sys/dev/ic/rtwn.c

2447

reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM);

sys/dev/ic/rtwn.c

2451

reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF);

sys/dev/ic/rtwn.c

2457

rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &

sys/dev/ic/rtwn.c

2461

reg = rtwn_bb_read(sc, 0x818);

sys/dev/ic/rtwn.c

2483

rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);

sys/dev/ic/rtwn.c

2485

rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);

sys/dev/ic/rtwn.c

2490

rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |

sys/dev/ic/rtwn.c

2494

reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/dev/ic/rtwn.c

2497

reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/dev/ic/rtwn.c

2502

reg = rtwn_bb_read(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT);

sys/dev/ic/rtwn.c

2508

reg = rtwn_bb_read(sc,

sys/dev/ic/rtwn.c

2515

rtwn_bb_read(sc, R92C_OFDM0_RXAFE) |

sys/dev/ic/rtwn.c

2519

rtwn_bb_read(sc, R88F_RX_DFIR) &

sys/dev/ic/rtwn.c

2521

reg = rtwn_bb_read(sc, R88F_RX_DFIR);

sys/dev/ic/rtwn.c

2621

status = rtwn_bb_read(sc, 0xeac);

sys/dev/ic/rtwn.c

2626

tx[0] = (rtwn_bb_read(sc, R92C_TX_POWER_BEFORE_IQK_A + offset) >> 16)

sys/dev/ic/rtwn.c

2628

tx[1] = (rtwn_bb_read(sc, R92C_TX_POWER_AFTER_IQK_A + offset) >> 16)

sys/dev/ic/rtwn.c

2636

rx[0] = (rtwn_bb_read(sc, R92C_RX_POWER_BEFORE_IQK_A_2 + offset) >> 16)

sys/dev/ic/rtwn.c

2638

rx[1] = (rtwn_bb_read(sc, R92C_RX_POWER_AFTER_IQK_A_2 + offset) >> 16)

sys/dev/ic/rtwn.c

2668

xa_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)) & 0xff;

sys/dev/ic/rtwn.c

2669

xb_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)) & 0xff;

sys/dev/ic/rtwn.c

2678

iq_cal_regs->adda[i] = rtwn_bb_read(sc, reg_adda[i]);

sys/dev/ic/rtwn.c

2697

rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);

sys/dev/ic/rtwn.c

2699

rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);

sys/dev/ic/rtwn.c

2701

rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0));

sys/dev/ic/rtwn.c

2703

rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));

sys/dev/ic/rtwn.c

2705

rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));

sys/dev/ic/rtwn.c

2707

rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));

sys/dev/ic/rtwn.c

2709

rtwn_bb_read(sc, R92C_CONFIG_ANT_A);

sys/dev/ic/rtwn.c

2711

rtwn_bb_read(sc, R92C_CONFIG_ANT_B);

sys/dev/ic/rtwn.c

2713

rtwn_bb_read(sc, R92C_CCK0_AFESETTING);

sys/dev/ic/rtwn.c

2720

hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0));

sys/dev/ic/rtwn.c

2735

rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)) | (1 << 10) |

sys/dev/ic/rtwn.c

2738

rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), rtwn_bb_read(sc,

sys/dev/ic/rtwn.c

2740

rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), rtwn_bb_read(sc,

sys/dev/ic/rtwn.c

2858

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));

sys/dev/ic/rtwn.c

2863

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));

sys/dev/ic/rtwn.c

2912

reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));

sys/dev/ic/rtwn.c

2921

reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD);

sys/dev/ic/rtwn.c

2932

reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain));

sys/dev/ic/rtwn.c

2937

reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));

sys/dev/ic/rtwn.c

2942

reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD);

sys/dev/ic/rtwn.c

2952

reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain));

sys/dev/ic/rtwn.c

2962

reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA);

sys/dev/ic/rtwn.c

2967

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE);

sys/dev/ic/rtwn.c

3290

reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/dev/ic/rtwn.c

3293

reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/dev/ic/rtwn.c

468

reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));

sys/dev/ic/rtwn.c

470

reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));

sys/dev/ic/rtwn.c

487

if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)

sys/dev/ic/rtwn.c

488

val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));

sys/dev/ic/rtwn.c

490

val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));

sys/dev/pci/if_rtwn.c

2225

reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO);

sys/dev/pci/if_rtwn.c

2229

reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO);

sys/dev/pci/if_rtwn.c

2233

reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);

sys/dev/pci/if_rtwn.c

2237

reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);

sys/dev/pci/if_rtwn.c

2241

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);

sys/dev/pci/if_rtwn.c

2245

reg = rtwn_bb_read(sc, 0xe74);

sys/dev/pci/if_rtwn.c

2248

reg = rtwn_bb_read(sc, 0xe78);

sys/dev/pci/if_rtwn.c

2251

reg = rtwn_bb_read(sc, 0xe7c);

sys/dev/pci/if_rtwn.c

2254

reg = rtwn_bb_read(sc, 0xe80);

sys/dev/pci/if_rtwn.c

2257

reg = rtwn_bb_read(sc, 0xe88);

sys/dev/pci/if_rtwn.c

2269

if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR)