Symbol: reg_num
sys/dev/pci/drm/amd/display/dc/dm_services.h
165
#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
sys/dev/pci/drm/amd/display/dc/dm_services.h
168
block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
sys/dev/pci/drm/amd/display/dc/dm_services.h
169
block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
sys/dev/pci/drm/amd/display/dc/dm_services.h
171
#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
sys/dev/pci/drm/amd/display/dc/dm_services.h
175
block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
sys/dev/pci/drm/amd/display/dc/dm_services.h
176
block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
100
.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
104
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
105
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
106
.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
111
.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
114
.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
117
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
118
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
119
.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
125
.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
128
.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
132
#define vupdate_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
133
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
134
.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
140
.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
148
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
149
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
150
.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
156
.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
162
.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
170
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
171
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
173
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
174
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
176
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
177
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
179
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
180
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
89
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
90
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
91
.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
97
.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
100
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
101
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
104
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
107
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
108
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
109
IRQ_REG_ENTRY(DCP, reg_num, \
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
112
.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
116
#define vupdate_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
117
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
118
IRQ_REG_ENTRY(CRTC, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
124
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
125
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
126
IRQ_REG_ENTRY(CRTC, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
130
.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
138
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
139
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
141
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
142
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
144
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
145
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
147
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
148
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
76
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
77
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
79
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
81
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
82
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
84
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
86
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
88
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
90
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
91
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
92
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
95
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
99
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
103
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
104
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
105
.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
111
.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
114
.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
118
#define vupdate_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
119
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
120
.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
126
.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
134
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
135
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
136
.enable_reg = mmLB ## reg_num ## _INT_MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
142
.ack_reg = mmLB ## reg_num ## _VBLANK_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
155
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
156
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
158
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
159
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
161
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
162
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
164
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
165
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
74
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
75
[DC_IRQ_SOURCE_INVALID + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
76
.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
82
.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
85
.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
89
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
90
[DC_IRQ_SOURCE_HPD6 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
91
.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
96
.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
99
.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
102
.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
105
.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
109
#define vupdate_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
110
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
111
.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
117
.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
125
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
126
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
127
.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
133
.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
139
.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
147
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
148
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
150
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
151
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
153
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
154
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
156
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
157
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
65
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
66
[DC_IRQ_SOURCE_INVALID + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
67
.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
73
.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
76
.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
80
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
81
[DC_IRQ_SOURCE_HPD6 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
82
.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
87
.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
90
.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
94
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
95
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
96
.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
173
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
174
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
176
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
178
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
179
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
181
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
183
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
185
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
187
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
188
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
189
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
192
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
196
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
197
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
198
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
201
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
204
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
205
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
206
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
215
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
216
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
217
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
223
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
224
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
225
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
231
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
232
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
233
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
244
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
245
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
247
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
248
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
250
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
251
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
253
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
254
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
176
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
177
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
179
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
181
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
182
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
184
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
186
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
188
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
192
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
193
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
194
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
197
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
201
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
202
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
203
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
206
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
209
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
210
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
211
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
220
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
221
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
222
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
228
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
229
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
230
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
236
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
237
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
238
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
249
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
250
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
252
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
253
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
255
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
256
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
258
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
259
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
125
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
126
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
128
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
130
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
131
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
133
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
135
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
137
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
139
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
140
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
141
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
144
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
148
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
149
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
150
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
153
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
156
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
157
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
158
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
164
#define vupdate_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
165
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
166
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
175
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
176
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
177
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
182
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
183
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
184
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
190
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
191
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
192
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
203
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
204
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
206
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
207
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
209
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
210
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
212
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
213
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
186
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
187
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
189
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
191
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
192
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
194
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
196
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
198
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
214
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
215
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
216
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
219
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
223
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
224
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
225
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
228
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
231
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
232
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
233
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
242
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
243
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
244
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
250
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
251
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
252
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
258
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
259
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
260
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
278
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
279
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
281
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
282
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
284
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
285
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
287
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
288
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
195
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
196
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
198
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
200
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
201
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
203
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
205
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
207
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
223
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
224
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
225
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
228
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
232
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
233
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
234
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
237
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
240
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
241
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
242
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
251
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
252
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
253
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
259
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
260
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
261
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
274
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
275
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
276
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
287
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
288
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
290
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
291
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
293
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
294
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
296
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
297
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
178
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
179
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
180
.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
182
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
183
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
185
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
186
.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
187
.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
210
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
211
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
212
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
215
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
219
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
220
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
221
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
224
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
227
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
228
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
229
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
238
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
239
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
240
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
246
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
247
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
248
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
254
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
255
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
256
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
264
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
265
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
267
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
268
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
270
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
271
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
273
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
274
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
121
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
122
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
123
.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
125
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
126
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
128
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
129
.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
130
.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
134
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
135
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
136
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
139
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
143
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
144
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
145
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
148
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
151
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
152
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
153
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
162
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
163
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
164
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
170
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
171
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
172
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
178
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
179
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
180
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
188
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
189
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
191
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
192
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
194
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
195
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
197
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
198
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
181
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
182
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
184
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
186
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
187
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
189
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
191
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
193
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
209
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
210
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
211
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
214
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
218
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
219
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
220
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
223
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
226
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
227
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
228
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
237
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
238
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
239
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
245
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
246
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
247
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
253
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
254
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
255
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
273
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
274
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
276
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
277
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
279
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
280
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
282
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
283
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
183
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
184
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
186
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
188
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
189
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
191
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
193
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
195
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
211
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
212
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
213
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
216
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
220
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
221
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
222
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
225
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
228
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
229
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
230
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
239
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
240
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
241
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
247
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
248
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
249
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
255
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
256
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
257
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
275
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
276
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
278
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
279
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
281
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
282
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
284
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
285
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
188
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
189
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
191
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
193
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
194
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
196
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
198
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
200
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
216
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
217
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
218
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
221
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
225
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
226
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
227
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
230
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
233
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
234
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
235
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
244
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
245
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
246
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
252
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
253
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
254
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
260
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
261
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
262
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
280
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
281
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
283
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
284
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
286
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
287
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
289
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
290
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
192
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
193
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
195
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
197
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
198
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
200
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
202
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
204
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
220
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
221
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
222
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
225
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
229
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
230
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
231
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
234
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
237
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
238
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
239
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
245
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
246
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
247
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
255
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
256
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
257
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
263
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
264
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
265
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
270
#define vline1_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
271
[DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
272
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
277
#define vline2_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
278
[DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
279
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
297
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
298
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
300
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
301
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
303
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
304
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
306
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
307
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
180
#define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
181
REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
182
REG_STRUCT[base + reg_num].enable_mask = \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
183
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
184
REG_STRUCT[base + reg_num].enable_value[0] = \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
185
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
186
REG_STRUCT[base + reg_num].enable_value[1] = \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
187
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
188
REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
189
REG_STRUCT[base + reg_num].ack_mask = \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
190
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
191
REG_STRUCT[base + reg_num].ack_value = \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
192
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
208
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
209
IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
212
REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
213
REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
215
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
216
IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
219
REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
220
REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
222
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
223
IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
226
REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
231
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
232
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
235
REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
237
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
238
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
241
REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
243
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
244
IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
247
REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
258
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
259
dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
261
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
262
dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
264
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
265
dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
267
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
268
dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
159
#define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
160
REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
161
REG_STRUCT[base + reg_num].enable_mask = \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
162
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
163
REG_STRUCT[base + reg_num].enable_value[0] = \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
164
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
165
REG_STRUCT[base + reg_num].enable_value[1] = \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
166
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
167
REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
168
REG_STRUCT[base + reg_num].ack_mask = \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
169
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
170
REG_STRUCT[base + reg_num].ack_value = \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
171
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
187
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
188
IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
191
REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
192
REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
194
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
195
IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
198
REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
199
REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
201
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
202
IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
205
REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
210
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
211
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
214
REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
216
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
217
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
220
REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
222
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
223
IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
226
REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
237
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
238
dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
240
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
241
dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
243
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
244
dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
246
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
247
dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
158
#define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
159
REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
160
REG_STRUCT[base + reg_num].enable_mask = \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
161
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
162
REG_STRUCT[base + reg_num].enable_value[0] = \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
163
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
164
REG_STRUCT[base + reg_num].enable_value[1] = \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
165
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
166
REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
167
REG_STRUCT[base + reg_num].ack_mask = \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
168
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
169
REG_STRUCT[base + reg_num].ack_value = \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
170
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
186
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
187
IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
190
REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
191
REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
193
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
194
IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
197
REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
198
REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
200
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
201
IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
204
REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
209
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
210
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
213
REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
215
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
216
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
219
REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
221
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
222
IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
225
REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
236
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
237
dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
239
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
240
dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
242
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
243
dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
245
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
246
dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
172
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
173
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
175
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
177
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
178
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
180
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
182
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
184
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
200
#define hpd_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
201
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
202
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
205
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
209
#define hpd_rx_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
210
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
211
IRQ_REG_ENTRY(HPD, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
214
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
217
#define pflip_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
218
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
219
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
225
#define vblank_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
226
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
227
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
235
#define vupdate_no_lock_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
236
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
237
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
243
#define vline0_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
244
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
245
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
250
#define vline1_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
251
[DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
252
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
257
#define vline2_int_entry(reg_num)\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
258
[DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
259
IRQ_REG_ENTRY(OTG, reg_num,\
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
277
#define i2c_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
278
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
280
#define dp_sink_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
281
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
283
#define gpio_pad_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
284
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
286
#define dc_underflow_int_entry(reg_num) \
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
287
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
248
settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
260
settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
272
settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
284
settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
302
if (settings->reg_num > 9)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
307
for (i = 0; i < settings->reg_num; i++) {
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
367
for (i = 0; i < settings->reg_num; i++) {
sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h
285
unsigned char reg_num;
sys/dev/pci/drm/radeon/evergreen.c
4156
u32 dws, data, i, j, k, reg_num;
sys/dev/pci/drm/radeon/evergreen.c
4298
reg_num = cs_data[i].section[j].reg_count;
sys/dev/pci/drm/radeon/evergreen.c
4307
data = 0x08000000 | (reg_num * 4);
sys/dev/pci/drm/radeon/evergreen.c
4311
for (k = 0; k < reg_num; k++) {
sys/dev/pci/drm/radeon/evergreen.c
4315
reg_list_mc_addr += reg_num * 4;
sys/dev/pci/drm/radeon/evergreen.c
4316
reg_list_blk_index += reg_num;