sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

304

cp110->offsets = reg_offsets[params->inst];

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

44

static const struct dce110_compressor_reg_offsets reg_offsets[] = {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

78

cp110->offsets = reg_offsets[crtc_inst];

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

402

cp110->offsets = reg_offsets[params->inst];

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

43

static const struct dce112_compressor_reg_offsets reg_offsets[] = {

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

254

tg110->derived_offsets = reg_offsets[instance];

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

51

static const struct dce110_timing_generator_offsets reg_offsets[] = {

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

236

tg110->derived_offsets = reg_offsets[instance];

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

51

static const struct dce110_timing_generator_offsets reg_offsets[] = {

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

43

static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

65

(reg + reg_offsets[id].crtc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

104

static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

120

(reg + reg_offsets[id].blnd)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

123

(reg + reg_offsets[id].crtc)

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

42

static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

63

(reg + reg_offsets[id].crtc)

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

55

static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

77

(reg + reg_offsets[id].crtc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1233

inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1581

set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false);

sys/dev/pci/drm/i915/gt/intel_lrc.c

941

set_offsets(regs, reg_offsets(engine), engine, inhibit);