sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1123

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1160

tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1161

WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1235

status = RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1278

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1309

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1387

regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1595

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1625

r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1670

WREG32_SOC15(VCN, i, regUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1681

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2048

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2070

ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2101

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

381

RREG32_SOC15(VCN, i, regUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

58

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1038

MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1200

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1202

WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1280

regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1315

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1384

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1415

r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1464

WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1472

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1691

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1711

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1739

regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

52

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

985

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1072

tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1073

WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1147

status = RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1191

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1257

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1288

r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1333

WREG32_SOC15(VCN, i, regUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1344

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1551

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1573

ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1604

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

334

RREG32_SOC15(VCN, i, regUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

58

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1019

r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1064

WREG32_SOC15(VCN, i, regUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1072

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1272

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1294

ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1325

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

298

RREG32_SOC15(VCN, i, regUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

42

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

793

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

829

tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

830

WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

875

status = RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

919

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

950

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

986

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1041

status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1085

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1120

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1160

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1189

r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1234

WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1239

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1392

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1410

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1438

if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

45

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

830

MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

995

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

996

WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);