sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1104

WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1107

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1294

WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1297

tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1583

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1755

return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

72

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1336

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1372

SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1507

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

66

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

970

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1017

WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1020

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1207

WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1210

tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1245

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1419

return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

72

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1143

return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

56

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

774

WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

777

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

935

WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

938

tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

977

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1105

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1108

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1151

SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1258

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

59

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

760

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

763

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);