raw_reg_write
raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
raw_reg_write(regs, GEN8_GT_IIR(0), iir);
raw_reg_write(regs, GEN8_GT_IIR(1), iir);
raw_reg_write(regs, GEN8_GT_IIR(3), iir);
raw_reg_write(regs, GEN8_GT_IIR(2), iir);
raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
raw_reg_write(regs, SDEIER, 0);
raw_reg_write(regs, GTIIR, gt_iir);
raw_reg_write(regs, DEIIR, de_iir);
raw_reg_write(regs, GEN6_PMIIR, pm_iir);
raw_reg_write(regs, DEIER, de_ier);
raw_reg_write(regs, SDEIER, sde_ier);
raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0);
raw_reg_write(regs, DG1_MSTR_TILE_INTR, val);
raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);