sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

386

WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

391

WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

233

ring->me, regSDMA0_QUEUE0_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

512

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

517

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

547

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

83

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

236

regSDMA0_QUEUE0_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

504

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

509

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

543

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

82

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),