sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5576

reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5587

WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5589

WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3963

reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3973

WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3975

WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3981

uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1674

reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1685

WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1687

WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);