sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

582

WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

592

WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

171

WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

181

WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1971

WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

897

reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1685

WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

740

reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

883

WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1448

reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1692

{SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

713

WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

212

IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

216

IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000000, 0x1c0000),

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

218

IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000001, 0x1c0000),

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

220

IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000100, 0x1c0000),

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

222

IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000101, 0x1c0000),

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

224

IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

356

if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) {

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

404

WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

429

WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX,