sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

340

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

198

reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

236

WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

333

reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

125

reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

236

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4407

WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4457

WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

191

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3284

WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3334

WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

152

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1993

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2051

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2104

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1535

WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1715

WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);