sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

309

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

205

WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

212

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4390

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4451

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

167

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3267

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3328

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

128

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1859

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1976

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2045

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2101

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2102

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1223

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1226

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1257

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1525

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1530

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1532

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1390

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1393

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1424

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1705

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1710

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1712

WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);