rdmsr_safe
rdmsr_safe(MSR_MISC_ENABLE, &msr) == 0 &&
rdmsr_safe(MSR_MISC_ENABLE, &msr) == 0 &&
if (rdmsr_safe(IA32_VMX_EPT_VPID_CAP, &msr) == 0 &&
int rdmsr_safe(u_int msr, uint64_t *);
rdmsr_safe(MSR_CORE_C3_RESIDENCY, &sc->sc_c3[0]);
rdmsr_safe(MSR_CORE_C6_RESIDENCY, &sc->sc_c6[0]);
rdmsr_safe(MSR_CORE_C7_RESIDENCY, &sc->sc_c7[0]);
rdmsr_safe(MSR_PKG_C2_RESIDENCY, &sc->sc_pc2[0]);
rdmsr_safe(MSR_PKG_C3_RESIDENCY, &sc->sc_pc3[0]);
rdmsr_safe(MSR_PKG_C6_RESIDENCY, &sc->sc_pc6[0]);
rdmsr_safe(MSR_PKG_C7_RESIDENCY, &sc->sc_pc7[0]);
rdmsr_safe(MSR_PKG_C8_RESIDENCY, &sc->sc_pc8[0]);
rdmsr_safe(MSR_PKG_C9_RESIDENCY, &sc->sc_pc9[0]);
rdmsr_safe(MSR_PKG_C10_RESIDENCY, &sc->sc_pc10[0]);
rdmsr_safe(sc->sc_counter[i].address, &sc->sc_lpit[i][0]);
rdmsr_safe(MSR_CORE_C3_RESIDENCY, &sc->sc_c3[1]);
rdmsr_safe(MSR_CORE_C6_RESIDENCY, &sc->sc_c6[1]);
rdmsr_safe(MSR_CORE_C7_RESIDENCY, &sc->sc_c7[1]);
rdmsr_safe(MSR_PKG_C2_RESIDENCY, &sc->sc_pc2[1]);
rdmsr_safe(MSR_PKG_C3_RESIDENCY, &sc->sc_pc3[1]);
rdmsr_safe(MSR_PKG_C6_RESIDENCY, &sc->sc_pc6[1]);
rdmsr_safe(MSR_PKG_C7_RESIDENCY, &sc->sc_pc7[1]);
rdmsr_safe(MSR_PKG_C8_RESIDENCY, &sc->sc_pc8[1]);
rdmsr_safe(MSR_PKG_C9_RESIDENCY, &sc->sc_pc9[1]);
rdmsr_safe(MSR_PKG_C10_RESIDENCY, &sc->sc_pc10[1]);
rdmsr_safe(sc->sc_counter[i].address, &sc->sc_lpit[i][1]);