rdmsr
msrv = rdmsr(msr);
msrv = rdmsr(msr);
msrv = rdmsr(msr);
msrv = rdmsr(msr);
msrv = rdmsr(msr + 1);
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800);
mtrrcap = rdmsr(MSR_MTRRcap);
mtrrdef = rdmsr(MSR_MTRRdefType);
msr = rdmsr(IA32_DEBUG_INTERFACE);
nmsr = msr = rdmsr(MSR_DE_CFG);
nmsr = msr = rdmsr(MSR_DE_CFG);
msr = rdmsr(MSR_S_CET);
msr = rdmsr(MSR_ARCH_CAPABILITIES);
msr = rdmsr(MSR_TSX_CTRL);
(rdmsr(MSR_ARCH_CAPABILITIES) & ARCH_CAP_IBRS_ALL)) {
cap = rdmsr(MSR_ARCH_CAPABILITIES);
gsb = rdmsr(MSR_GSBASE);
gsb = rdmsr(MSR_KERNELGSBASE);
msr = rdmsr(MSR_EBC_FREQUENCY_ID);
msr = rdmsr(MSR_FSB_FREQ);
msr = rdmsr(MSR_FSB_FREQ);
printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON));
msr = rdmsr(MSR_PERF_STATUS);
msr = rdmsr(MSR_PERF_STATUS);
msr = rdmsr(MSR_PERF_CTL);
msr = rdmsr(IA32_VMX_CR0_FIXED0);
msr = rdmsr(IA32_VMX_CR0_FIXED1);
msr = rdmsr(IA32_VMX_CR4_FIXED0);
msr = rdmsr(IA32_VMX_CR4_FIXED1);
msr = rdmsr(IA32_VMX_BASIC);
msr = rdmsr(IA32_VMX_MISC);
msr = rdmsr(MSR_AMD_VM_CR);
(rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) &
msr = rdmsr(MSR_ARCH_CAPABILITIES);
rdmsr(MSR_TEMPERATURE_TARGET));
msr = rdmsr(MSR_THERM_STATUS);
mperf = rdmsr(MSR_MPERF);
aperf = rdmsr(MSR_APERF);
msreg = rdmsr(0x110B);
msreg = rdmsr(0x1107);
msreg = rdmsr(0x1107);
msreg = rdmsr(0x1107);
msreg = rdmsr(0x1107);
msr = rdmsr(MSR_CENT_TMTEMPERATURE);
msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL);
msr = rdmsr(MSR_PERF_GLOBAL_CTRL) | MSR_PERF_GLOBAL_CTR1_EN;
last_count = rdmsr(MSR_PERF_FIXED_CTR1);
count = rdmsr(MSR_PERF_FIXED_CTR1);
msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL);
msr = rdmsr(MSR_PERF_GLOBAL_CTRL);
level = rdmsr(MSR_PATCH_LEVEL);
level = rdmsr(MSR_BIOS_SIGN) >> 32;
uint32_t msr = rdmsr(MSR_ARCH_CAPABILITIES);
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
msr = rdmsr(IA32_VMX_PROCBASED_CTLS);
msr = rdmsr(IA32_VMX_PROCBASED2_CTLS);
msr = rdmsr(MSR_K1X_STATUS);
return rdmsr(MSR_X2APIC_BASE + (reg >> 4));
msr = rdmsr(MSR_APICBASE);
msr = rdmsr(MSR_INT_PEN_MSG);
uint64_t msr = rdmsr(MSR_U_CET);
fn = rdmsr(msrsel + i);
st->pctr_fn[i] = rdmsr(reg + i);
*status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
(void *)rdmsr(MSR_GSBASE), (void *)rdmsr(MSR_KERNELGSBASE));
if (!ISSET(rdmsr(MSR_HWCR), HWCR_TSCFREQSEL))
def = rdmsr(MSR_PSTATEDEF(0));
tts->adj = rdmsr(MSR_TSC_ADJUST);
level = rdmsr(MSR_PATCH_LEVEL);
level = rdmsr(MSR_PATCH_LEVEL);
uint64_t platform_id = (rdmsr(MSR_PLATFORM_ID) >> 50) & 7;
rev = rdmsr(MSR_BIOS_SIGN);
vcpu->vc_vmx_basic = rdmsr(IA32_VMX_BASIC);
vcpu->vc_vmx_entry_ctls = rdmsr(IA32_VMX_ENTRY_CTLS);
vcpu->vc_vmx_exit_ctls = rdmsr(IA32_VMX_EXIT_CTLS);
vcpu->vc_vmx_pinbased_ctls = rdmsr(IA32_VMX_PINBASED_CTLS);
vcpu->vc_vmx_procbased_ctls = rdmsr(IA32_VMX_PROCBASED_CTLS);
vcpu->vc_vmx_true_entry_ctls = rdmsr(IA32_VMX_TRUE_ENTRY_CTLS);
vcpu->vc_vmx_true_exit_ctls = rdmsr(IA32_VMX_TRUE_EXIT_CTLS);
rdmsr(IA32_VMX_TRUE_PINBASED_CTLS);
rdmsr(IA32_VMX_TRUE_PROCBASED_CTLS);
vcpu->vc_vmx_procbased2_ctls = rdmsr(IA32_VMX_PROCBASED2_CTLS);
msr_misc_enable = rdmsr(MSR_MISC_ENABLE);
msr_store[VCPU_HOST_REGS_EFER].vms_data = rdmsr(MSR_EFER);
msr_store[VCPU_HOST_REGS_STAR].vms_data = rdmsr(MSR_STAR);
msr_store[VCPU_HOST_REGS_LSTAR].vms_data = rdmsr(MSR_LSTAR);
msr_store[VCPU_HOST_REGS_SFMASK].vms_data = rdmsr(MSR_SFMASK);
vcpu->vc_shadow_pat = rdmsr(MSR_CR_PAT);
msr = rdmsr(IA32_VMX_EPT_VPID_CAP);
vcpu->vc_shadow_pat = rdmsr(MSR_CR_PAT);
msr = rdmsr(MSR_FSBASE);
rdmsr(MSR_KERNELGSBASE);
msr = rdmsr(MSR_EFER);
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
msr = rdmsr(MSR_EFER);
req->val = rdmsr(req->addr);
gld_msr_cap = rdmsr(GLX_CPU_GLD_MSR_CAP);
gld_msr_cap = rdmsr(GLX_GP_GLD_MSR_CAP);
msr = rdmsr(MSR_ARCH_CAPABILITIES);
msr = rdmsr(MSR_TSX_CTRL);
msr = rdmsr(MSR_PERF_STATUS);
msr = rdmsr(MSR_PERF_STATUS);
msr = rdmsr(MSR_PERF_CTL);
msrv = rdmsr(msr);
msrv = rdmsr(msr);
msrv = rdmsr(msr);
msrv = rdmsr(msr);
msrv = rdmsr(msr + 1);
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRRdefType_ENABLE);
mtrrcap = rdmsr(MSR_MTRRcap);
mtrrdef = rdmsr(MSR_MTRRdefType);
msr = rdmsr(MSR_K1X_STATUS);
reg = rdmsr(UWCCR);
reg = rdmsr(UWCCR);
reg = rdmsr(UWCCR);
msr = rdmsr(MSR_INT_PEN_MSG);
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))
msreg = rdmsr(0x110B);
msreg = rdmsr(0x1107);
msreg = rdmsr(0x1107);
msreg = rdmsr(0x1107);
msreg = rdmsr(0x1107);
msr = rdmsr(MSR_C7M_TMTEMPERATURE);
msr = rdmsr(MSR_CENT_TMTEMPERATURE);
(rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) &
rdmsr(MSR_TEMPERATURE_TARGET));
msr = rdmsr(MSR_THERM_STATUS);
if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))
msr119 = rdmsr(MSR_BBL_CR_CTL);
level = rdmsr(MSR_PATCH_LEVEL);
level = rdmsr(MSR_BIOS_SIGN) >> 32;
nmsr = msr = rdmsr(MSR_DE_CFG);
nmsr = msr = rdmsr(MSR_DE_CFG);
msr = rdmsr(IA32_DEBUG_INTERFACE);
msr = rdmsr(MSR_EBL_CR_POWERON);
msr = rdmsr(MSR_EBC_FREQUENCY_ID);
msr = rdmsr(MSR_FSB_FREQ);
msr = rdmsr(MSR_FSB_FREQ);
msr = rdmsr(MSR_FSB_FREQ);
msr = rdmsr(MSR_EBL_CR_POWERON);
printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON));
msr = rdmsr(MSR_EBC_FREQUENCY_ID);
msr = rdmsr(MSR_EBL_CR_POWERON);
msreg = rdmsr(MSR_THERM_CONTROL);
vet = rdmsr(MSR_THERM_CONTROL);
msr11 = rdmsr(P5MSR_CTRSEL);
msr11 = rdmsr(P5MSR_CTRSEL);
st->pctr_hwc[0] = rdmsr(P5MSR_CTR0);
st->pctr_hwc[1] = rdmsr(P5MSR_CTR1);
st->pctr_fn[i] = rdmsr(reg + i);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
ctl = rdmsr(MSR_AMDK7_FIDVID_CTL) & PN7_CTR_FIDCHRATIO;
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
*status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
level = rdmsr(MSR_PATCH_LEVEL);
level = rdmsr(MSR_PATCH_LEVEL);
uint64_t platform_id = (rdmsr(MSR_PLATFORM_ID) >> 50) & 7;
rev = rdmsr(MSR_BIOS_SIGN);
static __inline u_int64_t rdmsr(u_int);
msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL);
msr = rdmsr(MSR_PERF_GLOBAL_CTRL) | MSR_PERF_GLOBAL_CTR1_EN;
last_count = rdmsr(MSR_PERF_FIXED_CTR1);
count = rdmsr(MSR_PERF_FIXED_CTR1);
msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL);
msr = rdmsr(MSR_PERF_GLOBAL_CTRL);
msr = rdmsr(SB_GLD_MSR_CAP);
msr = rdmsr(SB_GLD_MSR_CTRL);
sc->save_gld_msr = rdmsr(SB_GLD_MSR_CTRL);
reg = rdmsr(drive ? GCSC_ATAC_CH0D1_DMA :
msr = rdmsr(PIC_YSEL_LOW);
msr = rdmsr(PIC_YSEL_HIGH);
msr = rdmsr(GLPCI_GLD_MSR_ERROR);
msr = rdmsr(DIVIL_LBAR_SMB);
msr = rdmsr(GLCP_CHIP_REV_ID);
msr = rdmsr(GLPCI_CTRL);
data = (pcireg_t)rdmsr(pcib_bar_msr[index]);
msr = rdmsr(pcib_bar_msr[index]);
msr = rdmsr(GLPCI_GLD_MSR_ERROR);
msr = rdmsr(GLPCI_CTRL);
msr = rdmsr(GLIU_PAE);
msr = rdmsr(IDE_GLD_MSR_CAP);
msr = rdmsr(GLPCI_CTRL);
msr = rdmsr(IDE_IO_BAR);
data = rdmsr(IDE_CFG);
data = rdmsr(IDE_DTC);
data = rdmsr(IDE_ETC);
msr = rdmsr(GLIU_PAE);
msr = rdmsr(GLPCI_CTRL);
msr = rdmsr(GLIU_PAE);
msr = rdmsr(ACC_GLD_MSR_CAP);
msr = rdmsr(GLPCI_CTRL);
msr = rdmsr(GLIU_IOD_BM1);
msr = rdmsr(GLIU_PAE);
msr = rdmsr(GLPCI_CTRL);
msr = rdmsr(GLIU_IOD_BM1);
msr = rdmsr(USB_MSR_OHCB);
msr = rdmsr(USB_GLD_MSR_CAP);
msr = rdmsr(GLPCI_CTRL);
msr = rdmsr(USB_MSR_OHCB);
msr = rdmsr(USB_MSR_OHCB);
msr = rdmsr(GLPCI_CTRL);
msr = rdmsr(GLIU_P2D_BM3);
msr = rdmsr(USB_MSR_OHCB);
msr = rdmsr(USB_MSR_OHCB);
msr = rdmsr(USB_MSR_EHCB);
msr = rdmsr(USB_GLD_MSR_CAP);
msr = rdmsr(GLPCI_CTRL);
msr = rdmsr(USB_MSR_EHCB);
msr = rdmsr(USB_MSR_EHCB);
msr = rdmsr(USB_MSR_EHCB);
msr = rdmsr(GLPCI_CTRL);
msr = rdmsr(GLIU_P2D_BM4);
msr = rdmsr(USB_MSR_EHCB);
msr = rdmsr(USB_MSR_EHCB);
msr = rdmsr(DIVIL_BALL_OPTS); /* 0x71 */
wa = rdmsr(MSR_LBAR_MFGPT);
wa = rdmsr(MFGPT_IRQ);
wa = rdmsr(PIC_ZSEL_LOW);
gpiobase = BONITO_PCIIO_BASE + (rdmsr(DIVIL_LBAR_GPIO) & 0xff00);
wrmsr(GLCP_SYS_RST, rdmsr(GLCP_SYS_RST) | 1);
(int)rdmsr(AMD5536_REV) & AMD5536_REV_MASK,
wa = rdmsr(MSR_LBAR_MFGPT);
ga = rdmsr(MSR_LBAR_GPIO);
sa = rdmsr(MSR_LBAR_SMB);
sa = rdmsr(MSR_LBAR_PMS);
sc->sc_msrsave[i] = rdmsr(glxpcib_msrlist[i]);
return rdmsr(AMD5536_TMC);
rdmsr(AMD5536_MFGPT_NR) | AMD5536_MFGPT0_C2_RSTEN);
rdmsr(AMD5536_MFGPT_NR) & ~AMD5536_MFGPT0_C2_RSTEN);
uint64_t rdmsr(uint);
u_int now = rdmsr(MSR_HV_TIME_REF_COUNT);
start = rdmsr(MSR_HV_TIME_REF_COUNT);
while (rdmsr(MSR_HV_TIME_REF_COUNT) - start < interval)
if (!(rdmsr(MSR_HV_HYPERCALL) & MSR_HV_HYPERCALL_ENABLE)) {
simp = rdmsr(MSR_HV_SIMP);
siefp = rdmsr(MSR_HV_SIEFP);
sint = rdmsr(MSR_HV_SINT0 + VMBUS_SINT_MESSAGE);
sctrl = rdmsr(MSR_HV_SCONTROL);
sc->sc_vcpus[cpu] = rdmsr(MSR_HV_VP_INDEX);