que
struct em_queue *que = sc->queues; /* single queue */
em_txeof(que);
if (em_rxeof(que))
em_rxrefill_locked(que);
em_encap(struct em_queue *que, struct mbuf *m)
struct em_softc *sc = que->sc;
head = que->tx.sc_tx_desc_head;
pkt = &que->tx.sc_tx_pkts_ring[head];
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,
0, que->tx.sc_tx_dma.dma_map->dm_mapsize,
used += em_tso_setup(que, m, head, &txd_upper,
used += em_tx_ctx_setup(que, m, head, &txd_upper,
used += em_transmit_checksum_setup(que, m, head,
desc = &que->tx.sc_tx_desc_ring[head];
(que->tx.sc_txd_cmd | txd_lower |
desc = &que->tx.sc_tx_desc_ring[head];
desc->lower.data = htole32(que->tx.sc_txd_cmd |
que->tx.sc_tx_desc_head = head;
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,
0, que->tx.sc_tx_dma.dma_map->dm_mapsize,
struct em_queue *que = sc->queues; /* single queue chip */
hw_tdt = E1000_READ_REG(&sc->hw, TDT(que->me));
sw_tdt = que->tx.sc_tx_desc_head;
tx_desc = &que->tx.sc_tx_desc_ring[hw_tdt];
E1000_WRITE_REG(&sc->hw, TDT(que->me), hw_tdt);
struct em_queue *que = sc->queues; /* single queue chip */
if ((E1000_READ_REG(&sc->hw, TDT(que->me)) ==
E1000_READ_REG(&sc->hw, TDH(que->me))) &&
struct em_queue *que = sc->queues; /* Use only first queue. */
timeout_del(&que->rx_refill);
struct em_queue *que = NULL;
que = malloc(sizeof(struct em_queue), M_DEVBUF, M_NOWAIT | M_ZERO);
if (que == NULL) {
que->me = 0;
que->sc = sc;
timeout_set(&que->rx_refill, em_rxrefill, que);
sc->queues = que;
struct em_queue *que = NULL;
FOREACH_QUEUE(sc, que) {
if (que->rx.sc_rx_desc_ring != NULL) {
que->rx.sc_rx_desc_ring = NULL;
em_dma_free(sc, &que->rx.sc_rx_dma);
if (que->tx.sc_tx_desc_ring != NULL) {
que->tx.sc_tx_desc_ring = NULL;
em_dma_free(sc, &que->tx.sc_tx_dma);
if (que->tag)
pci_intr_disestablish(pc, que->tag);
que->tag = NULL;
que->eims = 0;
que->me = 0;
que->sc = NULL;
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,
0, que->tx.sc_tx_dma.dma_map->dm_mapsize,
que->tx.sc_tx_pkts_ring = mallocarray(sc->sc_tx_slots,
sizeof(*que->tx.sc_tx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO);
if (que->tx.sc_tx_pkts_ring == NULL) {
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
bzero((void *) que->tx.sc_tx_desc_ring,
pkt = &que->tx.sc_tx_pkts_ring[i];
que->tx.sc_tx_desc_head = 0;
que->tx.sc_tx_desc_tail = 0;
que->tx.active_checksum_context = OFFLOAD_NONE;
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
bus_addr = que->tx.sc_tx_dma.dma_map->dm_segs[0].ds_addr;
E1000_WRITE_REG(&sc->hw, TDLEN(que->me),
E1000_WRITE_REG(&sc->hw, TDBAH(que->me), (u_int32_t)(bus_addr >> 32));
E1000_WRITE_REG(&sc->hw, TDBAL(que->me), (u_int32_t)bus_addr);
E1000_WRITE_REG(&sc->hw, TDT(que->me), 0);
E1000_WRITE_REG(&sc->hw, TDH(que->me), 0);
E1000_READ_REG(&sc->hw, TDBAL(que->me)),
E1000_READ_REG(&sc->hw, TDLEN(que->me)));
que->tx.sc_txd_cmd = E1000_TXD_CMD_IFCS;
reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL(que->me));
E1000_WRITE_REG(&sc->hw, TXDCTL(que->me), reg_tctl);
que->tx.sc_txd_cmd |= E1000_TXD_CMD_IDE;
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
if (que->tx.sc_tx_pkts_ring != NULL) {
pkt = &que->tx.sc_tx_pkts_ring[i];
free(que->tx.sc_tx_pkts_ring, M_DEVBUF,
sc->sc_tx_slots * sizeof(*que->tx.sc_tx_pkts_ring));
que->tx.sc_tx_pkts_ring = NULL;
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,
0, que->tx.sc_tx_dma.dma_map->dm_mapsize,
em_tso_setup(struct em_queue *que, struct mbuf *mp, u_int head,
TD = (struct e1000_adv_tx_context_desc *)&que->tx.sc_tx_desc_ring[head];
if (que->sc->hw.mac_type == em_82575)
mss_l4len_idx |= (que->me & 0xff) << 4;
em_tx_ctx_setup(struct em_queue *que, struct mbuf *mp, u_int head,
TD = (struct e1000_adv_tx_context_desc *)&que->tx.sc_tx_desc_ring[head];
if (que->sc->hw.mac_type == em_82575)
mss_l4len_idx |= (que->me & 0xff) << 4;
em_transmit_checksum_setup(struct em_queue *que, struct mbuf *mp, u_int head,
if (que->tx.active_checksum_context == OFFLOAD_TCP_IP)
que->tx.active_checksum_context = OFFLOAD_TCP_IP;
if (que->tx.active_checksum_context == OFFLOAD_UDP_IP)
que->tx.active_checksum_context = OFFLOAD_UDP_IP;
TXD = (struct em_context_desc *)&que->tx.sc_tx_desc_ring[head];
if (que->tx.active_checksum_context == OFFLOAD_TCP_IP) {
} else if (que->tx.active_checksum_context == OFFLOAD_UDP_IP) {
TXD->cmd_and_length = htole32(que->tx.sc_txd_cmd | E1000_TXD_CMD_DEXT);
em_txeof(struct em_queue *que)
struct em_softc *sc = que->sc;
head = que->tx.sc_tx_desc_head;
tail = que->tx.sc_tx_desc_tail;
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,
0, que->tx.sc_tx_dma.dma_map->dm_mapsize,
pkt = &que->tx.sc_tx_pkts_ring[tail];
desc = &que->tx.sc_tx_desc_ring[pkt->pkt_eop];
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,
0, que->tx.sc_tx_dma.dma_map->dm_mapsize,
que->tx.sc_tx_desc_tail = tail;
em_get_buf(struct em_queue *que, int i)
struct em_softc *sc = que->sc;
pkt = &que->rx.sc_rx_pkts_ring[i];
desc = &que->rx.sc_rx_desc_ring[i];
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
que->rx.sc_rx_pkts_ring = mallocarray(sc->sc_rx_slots,
sizeof(*que->rx.sc_rx_pkts_ring),
if (que->rx.sc_rx_pkts_ring == NULL) {
bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,
0, que->rx.sc_rx_dma.dma_map->dm_mapsize,
pkt = &que->rx.sc_rx_pkts_ring[i];
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
memset(que->rx.sc_rx_desc_ring, 0,
sc->sc_rx_slots * sizeof(*que->rx.sc_rx_desc_ring));
que->rx.sc_rx_desc_tail = 0;
que->rx.sc_rx_desc_head = sc->sc_rx_slots - 1;
if_rxr_init(&que->rx.sc_rx_ring, lwm, sc->sc_rx_slots);
if (em_rxfill(que) == 0) {
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
reg_srrctl = E1000_READ_REG(&sc->hw, SRRCTL(que->me));
E1000_WRITE_REG(&sc->hw, SRRCTL(que->me), reg_srrctl);
bus_addr = que->rx.sc_rx_dma.dma_map->dm_segs[0].ds_addr;
E1000_WRITE_REG(&sc->hw, RDLEN(que->me),
sc->sc_rx_slots * sizeof(*que->rx.sc_rx_desc_ring));
E1000_WRITE_REG(&sc->hw, RDBAH(que->me), (u_int32_t)(bus_addr >> 32));
E1000_WRITE_REG(&sc->hw, RDBAL(que->me), (u_int32_t)bus_addr);
reg = E1000_READ_REG(&sc->hw, RXDCTL(que->me));
E1000_WRITE_REG(&sc->hw, RXDCTL(que->me), reg);
FOREACH_QUEUE(sc, que) {
E1000_WRITE_REG(&sc->hw, RDH(que->me), 0);
E1000_WRITE_REG(&sc->hw, RDT(que->me), que->rx.sc_rx_desc_head);
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
if_rxr_init(&que->rx.sc_rx_ring, 0, 0);
bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,
0, que->rx.sc_rx_dma.dma_map->dm_mapsize,
if (que->rx.sc_rx_pkts_ring != NULL) {
pkt = &que->rx.sc_rx_pkts_ring[i];
free(que->rx.sc_rx_pkts_ring, M_DEVBUF,
sc->sc_rx_slots * sizeof(*que->rx.sc_rx_pkts_ring));
que->rx.sc_rx_pkts_ring = NULL;
if (que->rx.fmp != NULL) {
m_freem(que->rx.fmp);
que->rx.fmp = NULL;
que->rx.lmp = NULL;
em_rxfill(struct em_queue *que)
struct em_softc *sc = que->sc;
i = que->rx.sc_rx_desc_head;
bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,
0, que->rx.sc_rx_dma.dma_map->dm_mapsize,
for (slots = if_rxr_get(&que->rx.sc_rx_ring, sc->sc_rx_slots);
if (em_get_buf(que, i) != 0)
que->rx.sc_rx_desc_head = i;
if_rxr_put(&que->rx.sc_rx_ring, slots);
bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,
0, que->rx.sc_rx_dma.dma_map->dm_mapsize,
struct em_queue *que = arg;
em_rxrefill_locked(que);
em_rxrefill_locked(struct em_queue *que)
struct em_softc *sc = que->sc;
if (em_rxfill(que))
E1000_WRITE_REG(&sc->hw, RDT(que->me), que->rx.sc_rx_desc_head);
else if (if_rxr_needrefill(&que->rx.sc_rx_ring))
timeout_add(&que->rx_refill, 1);
em_rxeof(struct em_queue *que)
struct em_softc *sc = que->sc;
if (if_rxr_inuse(&que->rx.sc_rx_ring) == 0)
i = que->rx.sc_rx_desc_tail;
bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,
0, que->rx.sc_rx_dma.dma_map->dm_mapsize,
pkt = &que->rx.sc_rx_pkts_ring[i];
desc = &que->rx.sc_rx_desc_ring[i];
if_rxr_put(&que->rx.sc_rx_ring, 1);
if (que->rx.fmp != NULL)
pkt_len += que->rx.fmp->m_pkthdr.len;
if (que->rx.fmp == NULL) {
que->rx.fmp = m; /* Store the first mbuf */
que->rx.lmp = m;
que->rx.lmp->m_len -= prev_len_adj;
que->rx.fmp->m_pkthdr.len -= prev_len_adj;
que->rx.lmp->m_next = m;
que->rx.lmp = m;
que->rx.fmp->m_pkthdr.len += m->m_len;
m = que->rx.fmp;
que->rx.fmp = NULL;
que->rx.lmp = NULL;
que->rx.dropped_pkts++;
if (que->rx.fmp != NULL) {
m_freem(que->rx.fmp);
que->rx.fmp = NULL;
que->rx.lmp = NULL;
} while (if_rxr_inuse(&que->rx.sc_rx_ring) > 0);
bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,
0, que->rx.sc_rx_dma.dma_map->dm_mapsize,
que->rx.sc_rx_desc_tail = i;
if_rxr_livelocked(&que->rx.sc_rx_ring);
em_flush_tx_ring(struct em_queue *que)
struct em_softc *sc = que->sc;
KASSERT(que->tx.sc_tx_desc_ring != NULL);
KASSERT(EM_READ_REG(&sc->hw, E1000_TDT(que->me)) == que->tx.sc_tx_desc_head);
txd = &que->tx.sc_tx_desc_ring[que->tx.sc_tx_desc_head];
txd->buffer_addr = que->tx.sc_tx_dma.dma_map->dm_segs[0].ds_addr;
if (++que->tx.sc_tx_desc_head == sc->sc_tx_slots)
que->tx.sc_tx_desc_head = 0;
EM_WRITE_REG(&sc->hw, E1000_TDT(que->me), que->tx.sc_tx_desc_head);
em_flush_rx_ring(struct em_queue *que)
struct em_softc *sc = que->sc;
rxdctl = EM_READ_REG(&sc->hw, E1000_RXDCTL(que->me));
EM_WRITE_REG(&sc->hw, E1000_RXDCTL(que->me), rxdctl);
struct em_queue *que = sc->queues; /* Use only first queue. */
tdlen = EM_READ_REG(&sc->hw, E1000_TDLEN(que->me));
em_flush_tx_ring(que);
em_flush_rx_ring(que);
struct em_queue *que = sc->queues; /* Use only first queue. */
que->me = vec;
que->eims = 1 << vec;
snprintf(que->name, sizeof(que->name), "%s:%d", DEVNAME(sc), vec);
que->tag = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE,
em_queue_intr_msix, que, que->name);
if (que->tag == NULL) {
struct em_queue *que = vque;
struct em_softc *sc = que->sc;
em_txeof(que);
if (em_rxeof(que))
em_rxrefill_locked(que);
em_enable_queue_intr_msix(que);
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
index = que->me >> 1;
if (que->me & 1) {
ivar |= (que->me | E1000_IVAR_VALID) << 16;
ivar |= que->me | E1000_IVAR_VALID;
FOREACH_QUEUE(sc, que) {
index = que->me >> 1;
if (que->me & 1) {
ivar |= (que->me | E1000_IVAR_VALID) << 24;
ivar |= (que->me | E1000_IVAR_VALID) << 8;
sc->msix_queuesmask |= que->eims;
FOREACH_QUEUE(sc, que) {
index = que->me & 0x7; /* Each IVAR has two entries */
if (que->me < 8) {
ivar |= que->me | E1000_IVAR_VALID;
ivar |= (que->me | E1000_IVAR_VALID) << 16;
sc->msix_queuesmask |= que->eims;
FOREACH_QUEUE(sc, que) {
index = que->me & 0x7; /* Each IVAR has two entries */
if (que->me < 8) {
ivar |= (que->me | E1000_IVAR_VALID) << 8;
ivar |= (que->me | E1000_IVAR_VALID) << 24;
sc->msix_queuesmask |= que->eims;
FOREACH_QUEUE(sc, que)
E1000_WRITE_REG(&sc->hw, EITR(que->me), newitr);
em_enable_queue_intr_msix(struct em_queue *que)
E1000_WRITE_REG(&que->sc->hw, EIMS, que->eims);
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
&que->tx.sc_tx_dma) != 0) {
que->tx.sc_tx_desc_ring =
(struct em_tx_desc *)que->tx.sc_tx_dma.dma_vaddr;
&que->rx.sc_rx_dma) != 0) {
que->rx.sc_rx_desc_ring =
(struct em_rx_desc *)que->rx.sc_rx_dma.dma_vaddr;
struct em_queue *que = sc->queues; /* Use only first queue. */
head = que->tx.sc_tx_desc_head;
free = que->tx.sc_tx_desc_tail;
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,
0, que->tx.sc_tx_dma.dma_map->dm_mapsize,
used = em_encap(que, m);
E1000_WRITE_REG(&sc->hw, TDT(que->me),
que->tx.sc_tx_desc_head);
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,
0, que->tx.sc_tx_dma.dma_map->dm_mapsize,
E1000_WRITE_REG(&sc->hw, TDT(que->me),
que->tx.sc_tx_desc_head);
struct em_queue *que = sc->queues; /* Use only first queue. */
que->tx.sc_tx_desc_head, que->tx.sc_tx_desc_tail,
E1000_READ_REG(&sc->hw, TDH(que->me)),
E1000_READ_REG(&sc->hw, TDT(que->me)));
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
reg_txdctl = E1000_READ_REG(hw, TXDCTL(que->me));
E1000_WRITE_REG(hw, TXDCTL(que->me), reg_txdctl);
struct em_queue *que;
FOREACH_QUEUE(sc, que) {
ctrl = E1000_READ_REG(hw, TXDCTL(que->me));
E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl);
struct ix_queue *que;
for (i = 0, que = sc->queues; i < sc->num_queues; i++, que++)
ixgbe_enable_queue(sc, que->msix);
struct ix_queue *que = vque;
struct ix_softc *sc = que->sc;
struct ix_rxring *rxr = que->rxr;
struct ix_txring *txr = que->txr;
ixgbe_enable_queue(sc, que->msix);
struct ix_queue *que;
for (i = 0, que = sc->queues; i < sc->num_queues; i++, que++) {
que->tag = pci_intr_establish_cpu(pa->pa_pc, ih,
ixgbe_queue_intr, que, que->name);
if (que->tag == NULL) {
que->msix = i;
for (que = sc->queues; i > 0; i--, que++) {
if (que->tag == NULL)
pci_intr_disestablish(pa->pa_pc, que->tag);
que->tag = NULL;
struct ix_queue *que = sc->queues;
for (i = 0; i < sc->num_queues; i++, que++) {
if (que->tag)
pci_intr_disestablish(pa->pa_pc, que->tag);
que->tag = NULL;
struct ix_queue *que;
que = &sc->queues[i];
que->sc = sc;
que->txr = &sc->tx_rings[i];
que->rxr = &sc->rx_rings[i];
snprintf(que->name, sizeof(que->name), "%s:%d",
struct ix_queue *que = sc->queues;
for (i = 0; i < sc->num_queues; i++, que++) {
ixgbe_set_ivar(sc, i, que->msix, 0);
ixgbe_set_ivar(sc, i, que->msix, 1);
IXGBE_EITR(que->msix), newitr);
struct ix_queue *que = sc->queues;
for (i = 0; i < sc->num_queues; i++, que++)
mask |= (1 << que->msix);
que = sc->queues;
for (i = 0; i < sc->num_queues; i++, que++)
ixv_enable_queue(sc, que->msix);
struct ix_queue *que = sc->queues;
for (i = 0; i < sc->num_queues; i++, que++) {
ixv_set_ivar(sc, i, que->msix, 0);
ixv_set_ivar(sc, i, que->msix, 1);
IXGBE_WRITE_REG(&sc->hw, IXGBE_VTEITR(que->msix),
struct ix_queue *que;
for (i = 0, que = sc->queues; i < sc->num_queues; i++, que++) {
que->tag = pci_intr_establish_cpu(pa->pa_pc, ih,
ixv_msix_que, que, que->name);
if (que->tag == NULL) {
que->msix = i;
for (que = sc->queues; i > 0; i--, que++) {
if (que->tag == NULL)
pci_intr_disestablish(pa->pa_pc, que->tag);
que->tag = NULL;
struct ix_queue *que = sc->queues;
for (i = 0; i < sc->num_queues; i++, que++)
mask |= (1 << que->msix);
struct ix_queue *que = arg;
struct ix_softc *sc = que->sc;
struct ix_txring *txr = que->txr;
struct ix_rxring *rxr = que->rxr;
ixv_disable_queue(sc, que->msix);
ixv_enable_queue(sc, que->msix);
struct que *que;
if ((que = que_lookup(msqid)) == NULL)
QREF(que);
if ((error = ipcperm(cred, &que->msqid_ds.msg_perm, IPC_M)))
TAILQ_REMOVE(&msg_queues, que, que_next);
que->que_flags |= MSGQ_DYING;
if (--que->que_references > 0) {
wakeup(que);
tsleep_nsec(&que->que_references, PZERO, "msgqrm",
que_free(que);
if ((error = ipcperm(cred, &que->msqid_ds.msg_perm, IPC_M)))
if (tmp.msg_qbytes > que->msqid_ds.msg_qbytes &&
que->msqid_ds.msg_perm.uid = tmp.msg_perm.uid;
que->msqid_ds.msg_perm.gid = tmp.msg_perm.gid;
que->msqid_ds.msg_perm.mode =
(que->msqid_ds.msg_perm.mode & ~0777) |
que->msqid_ds.msg_qbytes = tmp.msg_qbytes;
que->msqid_ds.msg_ctime = gettime();
if ((error = ipcperm(cred, &que->msqid_ds.msg_perm, IPC_R)))
error = copyout(&que->msqid_ds, umsq, sizeof(struct msqid_ds));
QRELE(que);
struct que *que;
que = que_key_lookup(key);
if (que) {
if ((error = ipcperm(cred, &que->msqid_ds.msg_perm,
if ((que = que_create(key, cred, msgflg & 0777)) == NULL)
*retval = IXSEQ_TO_IPCID(que->que_ix, que->msqid_ds.msg_perm);
struct que *que;
if ((que = que_lookup(SCARG(uap, msqid))) == NULL)
if (msgsz > que->msqid_ds.msg_qbytes || msgsz > msginfo.msgmax)
if ((error = ipcperm(cred, &que->msqid_ds.msg_perm, IPC_W)))
QREF(que);
while (MSGQ_SPACE(que) < msgsz || num_msgs >= msginfo.msgtql) {
que->que_flags |= MSGQ_WRITERS;
if ((error = tsleep_nsec(que, PZERO|PCATCH, "msgwait", INFSLP)))
if (que->que_flags & MSGQ_DYING) {
if ((msg = msg_create(que)) == NULL) {
msg_enqueue(que, msg, p);
if (que->que_flags & MSGQ_READERS) {
que->que_flags &= ~MSGQ_READERS;
wakeup(que);
if (que->que_flags & MSGQ_DYING) {
wakeup(que);
QRELE(que);
struct que *que;
if ((que = que_lookup(SCARG(uap, msqid))) == NULL)
if ((error = ipcperm(cred, &que->msqid_ds.msg_perm, IPC_R)))
QREF(que);
while ((msg = msg_lookup(que, msgtyp)) == NULL) {
que->que_flags |= MSGQ_READERS;
if ((error = tsleep_nsec(que, PZERO|PCATCH, "msgwait", INFSLP)))
if (que->que_flags & MSGQ_DYING) {
if (que->que_flags & MSGQ_RCVWAIT) {
que->que_flags |= MSGQ_RCVWAITING;
error = tsleep_nsec(&que->que_flags, PZERO | PCATCH,
if (que->que_flags & MSGQ_DYING) {
que->que_flags |= MSGQ_RCVWAIT;
msg_dequeue(que, msg, p);
if (que->que_flags & MSGQ_WRITERS) {
que->que_flags &= ~MSGQ_WRITERS;
wakeup(que);
que->que_flags &= ~MSGQ_RCVWAIT;
if (que->que_flags & MSGQ_RCVWAITING) {
que->que_flags &= ~MSGQ_RCVWAITING;
if (que->que_flags & MSGQ_DYING)
wakeup(&que->que_flags);
wakeup_one(&que->que_flags);
QRELE(que);
struct que *
struct que *que, *que2;
que = malloc(sizeof(*que), M_TEMP, M_WAIT|M_ZERO);
free(que, M_TEMP, sizeof *que);
que->que_ix = nextix;
que->msqid_ds.msg_perm.key = key;
que->msqid_ds.msg_perm.cuid = cred->cr_uid;
que->msqid_ds.msg_perm.uid = cred->cr_uid;
que->msqid_ds.msg_perm.cgid = cred->cr_gid;
que->msqid_ds.msg_perm.gid = cred->cr_gid;
que->msqid_ds.msg_perm.mode = mode & 0777;
que->msqid_ds.msg_perm.seq = ++sequence & 0x7fff;
que->msqid_ds.msg_qbytes = msginfo.msgmnb;
que->msqid_ds.msg_ctime = gettime();
TAILQ_INIT(&que->que_msgs);
TAILQ_INSERT_BEFORE(que2, que, que_next);
TAILQ_INSERT_TAIL(&msg_queues, que, que_next);
return (que);
struct que *
struct que *que;
TAILQ_FOREACH(que, &msg_queues, que_next)
if (que->que_ix == IPCID_TO_IX(id))
if (que && que->que_flags & MSGQ_DYING)
return (que);
struct que *
struct que *que;
TAILQ_FOREACH(que, &msg_queues, que_next)
if (que->msqid_ds.msg_perm.key == key)
if (que && que->que_flags & MSGQ_DYING)
return (que);
struct que *que_create(key_t, struct ucred *, int);
struct que *que;
TAILQ_FOREACH(que, &msg_queues, que_next) {
if (que->que_flags & MSGQ_WRITERS) {
que->que_flags &= ~MSGQ_WRITERS;
wakeup(que);
struct que *que_lookup(int);
que_free(struct que *que)
if (que->que_references > 0)
while ((msg = TAILQ_FIRST(&que->que_msgs))) {
struct que *que_key_lookup(key_t);
TAILQ_REMOVE(&que->que_msgs, msg, msg_next);
free(que, M_TEMP, sizeof *que);
msg_create(struct que *que)
if (que->que_flags & MSGQ_DYING) {
void que_free(struct que *);
wakeup(que);
struct msg *msg_create(struct que *);
msg_lookup(struct que *que, int msgtyp)
TAILQ_FOREACH(msg, &que->que_msgs, msg_next)
void msg_enqueue(struct que *, struct msg *, struct proc *);
msg_enqueue(struct que *que, struct msg *msg, struct proc *p)
void msg_dequeue(struct que *, struct msg *, struct proc *);
que->msqid_ds.msg_cbytes += msg->msg_len;
que->msqid_ds.msg_qnum++;
que->msqid_ds.msg_lspid = p->p_p->ps_pid;
que->msqid_ds.msg_stime = gettime();
TAILQ_INSERT_TAIL(&que->que_msgs, msg, msg_next);
msg_dequeue(struct que *que, struct msg *msg, struct proc *p)
struct msg *msg_lookup(struct que *, int);
que->msqid_ds.msg_cbytes -= msg->msg_len;
que->msqid_ds.msg_qnum--;
que->msqid_ds.msg_lrpid = p->p_p->ps_pid;
que->msqid_ds.msg_rtime = gettime();
TAILQ_REMOVE(&que->que_msgs, msg, msg_next);
struct que *que;
TAILQ_HEAD(, que) msg_queues;
TAILQ_FOREACH(que, &msg_queues, que_next)
memcpy(&info->msgids[que->que_ix], &que->msqid_ds,
TAILQ_ENTRY(que) que_next;
struct que msgque;