sys/dev/pci/drm/radeon/atombios_crtc.c

1001

&radeon_crtc->ss,

sys/dev/pci/drm/radeon/atombios_crtc.c

1004

radeon_crtc->ss_enabled =

sys/dev/pci/drm/radeon/atombios_crtc.c

1006

&radeon_crtc->ss,

sys/dev/pci/drm/radeon/atombios_crtc.c

1010

radeon_crtc->ss_enabled = false;

sys/dev/pci/drm/radeon/atombios_crtc.c

1015

radeon_crtc->ss_enabled =

sys/dev/pci/drm/radeon/atombios_crtc.c

1017

&radeon_crtc->ss,

sys/dev/pci/drm/radeon/atombios_crtc.c

1021

radeon_crtc->ss_enabled =

sys/dev/pci/drm/radeon/atombios_crtc.c

1023

&radeon_crtc->ss,

sys/dev/pci/drm/radeon/atombios_crtc.c

1028

radeon_crtc->ss_enabled =

sys/dev/pci/drm/radeon/atombios_crtc.c

1030

&radeon_crtc->ss,

sys/dev/pci/drm/radeon/atombios_crtc.c

1036

radeon_crtc->ss_enabled =

sys/dev/pci/drm/radeon/atombios_crtc.c

1038

&radeon_crtc->ss,

sys/dev/pci/drm/radeon/atombios_crtc.c

1048

radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);

sys/dev/pci/drm/radeon/atombios_crtc.c

1055

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1059

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

1064

int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

1069

(radeon_crtc->bpc > 8))

sys/dev/pci/drm/radeon/atombios_crtc.c

107

args.ucScaler = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

1070

clock = radeon_crtc->adjusted_clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

1072

switch (radeon_crtc->pll_id) {

sys/dev/pci/drm/radeon/atombios_crtc.c

1087

pll->flags = radeon_crtc->pll_flags;

sys/dev/pci/drm/radeon/atombios_crtc.c

1088

pll->reference_div = radeon_crtc->pll_reference_div;

sys/dev/pci/drm/radeon/atombios_crtc.c

1089

pll->post_div = radeon_crtc->pll_post_div;

sys/dev/pci/drm/radeon/atombios_crtc.c

1093

radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,

sys/dev/pci/drm/radeon/atombios_crtc.c

1096

radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,

sys/dev/pci/drm/radeon/atombios_crtc.c

1099

radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,

sys/dev/pci/drm/radeon/atombios_crtc.c

1102

atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,

sys/dev/pci/drm/radeon/atombios_crtc.c

1103

radeon_crtc->crtc_id, &radeon_crtc->ss);

sys/dev/pci/drm/radeon/atombios_crtc.c

1105

atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

sys/dev/pci/drm/radeon/atombios_crtc.c

1108

radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);

sys/dev/pci/drm/radeon/atombios_crtc.c

1110

if (radeon_crtc->ss_enabled) {

sys/dev/pci/drm/radeon/atombios_crtc.c

1115

(u32)radeon_crtc->ss.percentage) /

sys/dev/pci/drm/radeon/atombios_crtc.c

1116

(100 * (u32)radeon_crtc->ss.percentage_divider);

sys/dev/pci/drm/radeon/atombios_crtc.c

1117

radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;

sys/dev/pci/drm/radeon/atombios_crtc.c

1118

radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &

sys/dev/pci/drm/radeon/atombios_crtc.c

1120

if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)

sys/dev/pci/drm/radeon/atombios_crtc.c

1121

step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

sys/dev/pci/drm/radeon/atombios_crtc.c

1124

step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

sys/dev/pci/drm/radeon/atombios_crtc.c

1126

radeon_crtc->ss.step = step_size;

sys/dev/pci/drm/radeon/atombios_crtc.c

1129

atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,

sys/dev/pci/drm/radeon/atombios_crtc.c

1130

radeon_crtc->crtc_id, &radeon_crtc->ss);

sys/dev/pci/drm/radeon/atombios_crtc.c

1138

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1357

switch (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/atombios_crtc.c

1383

WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1385

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1387

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1389

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1391

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1393

WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);

sys/dev/pci/drm/radeon/atombios_crtc.c

1394

WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);

sys/dev/pci/drm/radeon/atombios_crtc.c

1401

WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1408

WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1409

WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1410

WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1411

WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1412

WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);

sys/dev/pci/drm/radeon/atombios_crtc.c

1413

WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);

sys/dev/pci/drm/radeon/atombios_crtc.c

1416

WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/pci/drm/radeon/atombios_crtc.c

1417

WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

sys/dev/pci/drm/radeon/atombios_crtc.c

142

switch (radeon_crtc->rmx_type) {

sys/dev/pci/drm/radeon/atombios_crtc.c

1420

WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1423

WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1427

WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1434

WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1438

WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1459

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1589

if (radeon_crtc->crtc_id == 0)

sys/dev/pci/drm/radeon/atombios_crtc.c

1597

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1600

if (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/atombios_crtc.c

1608

WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1611

radeon_crtc->crtc_offset, (u32) fb_location);

sys/dev/pci/drm/radeon/atombios_crtc.c

1612

WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);

sys/dev/pci/drm/radeon/atombios_crtc.c

1614

WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);

sys/dev/pci/drm/radeon/atombios_crtc.c

1617

WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1623

WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1624

WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1625

WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1626

WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

1627

WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);

sys/dev/pci/drm/radeon/atombios_crtc.c

1628

WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);

sys/dev/pci/drm/radeon/atombios_crtc.c

163

atom_rv515_force_tv_scaler(rdev, radeon_crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1631

WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/pci/drm/radeon/atombios_crtc.c

1632

WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

sys/dev/pci/drm/radeon/atombios_crtc.c

1634

WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1638

WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1642

WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_crtc.c

1646

WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);

sys/dev/pci/drm/radeon/atombios_crtc.c

169

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1697

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1700

switch (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/atombios_crtc.c

1727

struct radeon_crtc *test_radeon_crtc;

sys/dev/pci/drm/radeon/atombios_crtc.c

1755

struct radeon_crtc *test_radeon_crtc;

sys/dev/pci/drm/radeon/atombios_crtc.c

178

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

1785

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1789

struct radeon_crtc *test_radeon_crtc;

sys/dev/pci/drm/radeon/atombios_crtc.c

1792

adjusted_clock = radeon_crtc->adjusted_clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

1808

if (test_radeon_crtc->connector == radeon_crtc->connector) {

sys/dev/pci/drm/radeon/atombios_crtc.c

1817

(radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&

sys/dev/pci/drm/radeon/atombios_crtc.c

186

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1864

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1868

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

1873

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

sys/dev/pci/drm/radeon/atombios_crtc.c

1920

else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

sys/dev/pci/drm/radeon/atombios_crtc.c

194

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

1947

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

sys/dev/pci/drm/radeon/atombios_crtc.c

1970

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

sys/dev/pci/drm/radeon/atombios_crtc.c

2016

return radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

202

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

2045

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

2049

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

2056

if (!radeon_crtc->adjusted_clock)

sys/dev/pci/drm/radeon/atombios_crtc.c

2070

if (radeon_crtc->crtc_id == 0)

sys/dev/pci/drm/radeon/atombios_crtc.c

2079

radeon_crtc->hw_mode = *adjusted_mode;

sys/dev/pci/drm/radeon/atombios_crtc.c

2088

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

2095

radeon_crtc->encoder = encoder;

sys/dev/pci/drm/radeon/atombios_crtc.c

2096

radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

210

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

2100

if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {

sys/dev/pci/drm/radeon/atombios_crtc.c

2101

radeon_crtc->encoder = NULL;

sys/dev/pci/drm/radeon/atombios_crtc.c

2102

radeon_crtc->connector = NULL;

sys/dev/pci/drm/radeon/atombios_crtc.c

2105

if (radeon_crtc->encoder) {

sys/dev/pci/drm/radeon/atombios_crtc.c

2107

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

2109

radeon_crtc->output_csc = radeon_encoder->output_csc;

sys/dev/pci/drm/radeon/atombios_crtc.c

2116

radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

2118

if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&

sys/dev/pci/drm/radeon/atombios_crtc.c

2119

!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))

sys/dev/pci/drm/radeon/atombios_crtc.c

2146

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

2168

WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

2170

WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_crtc.c

2178

i != radeon_crtc->crtc_id &&

sys/dev/pci/drm/radeon/atombios_crtc.c

2179

radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {

sys/dev/pci/drm/radeon/atombios_crtc.c

2187

switch (radeon_crtc->pll_id) {

sys/dev/pci/drm/radeon/atombios_crtc.c

2191

atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

sys/dev/pci/drm/radeon/atombios_crtc.c

2200

atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

sys/dev/pci/drm/radeon/atombios_crtc.c

2207

radeon_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/pci/drm/radeon/atombios_crtc.c

2208

radeon_crtc->adjusted_clock = 0;

sys/dev/pci/drm/radeon/atombios_crtc.c

2209

radeon_crtc->encoder = NULL;

sys/dev/pci/drm/radeon/atombios_crtc.c

2210

radeon_crtc->connector = NULL;

sys/dev/pci/drm/radeon/atombios_crtc.c

2226

struct radeon_crtc *radeon_crtc)

sys/dev/pci/drm/radeon/atombios_crtc.c

2231

switch (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/atombios_crtc.c

2234

radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/atombios_crtc.c

2237

radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/atombios_crtc.c

2240

radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/atombios_crtc.c

2243

radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/atombios_crtc.c

2246

radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/atombios_crtc.c

2249

radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/atombios_crtc.c

2253

if (radeon_crtc->crtc_id == 1)

sys/dev/pci/drm/radeon/atombios_crtc.c

2254

radeon_crtc->crtc_offset =

sys/dev/pci/drm/radeon/atombios_crtc.c

2257

radeon_crtc->crtc_offset = 0;

sys/dev/pci/drm/radeon/atombios_crtc.c

2259

radeon_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/pci/drm/radeon/atombios_crtc.c

2260

radeon_crtc->adjusted_clock = 0;

sys/dev/pci/drm/radeon/atombios_crtc.c

2261

radeon_crtc->encoder = NULL;

sys/dev/pci/drm/radeon/atombios_crtc.c

2262

radeon_crtc->connector = NULL;

sys/dev/pci/drm/radeon/atombios_crtc.c

2263

drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);

sys/dev/pci/drm/radeon/atombios_crtc.c

228

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

238

vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);

sys/dev/pci/drm/radeon/atombios_crtc.c

239

WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);

sys/dev/pci/drm/radeon/atombios_crtc.c

242

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

248

WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);

sys/dev/pci/drm/radeon/atombios_crtc.c

253

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

261

args.ucDispPipeId = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

271

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

275

radeon_crtc->enabled = true;

sys/dev/pci/drm/radeon/atombios_crtc.c

280

if (dev->num_crtcs > radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/atombios_crtc.c

287

if (dev->num_crtcs > radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/atombios_crtc.c

289

if (radeon_crtc->enabled)

sys/dev/pci/drm/radeon/atombios_crtc.c

294

radeon_crtc->enabled = false;

sys/dev/pci/drm/radeon/atombios_crtc.c

305

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

313

args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));

sys/dev/pci/drm/radeon/atombios_crtc.c

315

cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));

sys/dev/pci/drm/radeon/atombios_crtc.c

316

args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));

sys/dev/pci/drm/radeon/atombios_crtc.c

318

cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));

sys/dev/pci/drm/radeon/atombios_crtc.c

320

cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);

sys/dev/pci/drm/radeon/atombios_crtc.c

324

cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);

sys/dev/pci/drm/radeon/atombios_crtc.c

327

args.ucH_Border = radeon_crtc->h_border;

sys/dev/pci/drm/radeon/atombios_crtc.c

328

args.ucV_Border = radeon_crtc->v_border;

sys/dev/pci/drm/radeon/atombios_crtc.c

344

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

352

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

371

args.ucOverscanRight = radeon_crtc->h_border;

sys/dev/pci/drm/radeon/atombios_crtc.c

372

args.ucOverscanLeft = radeon_crtc->h_border;

sys/dev/pci/drm/radeon/atombios_crtc.c

373

args.ucOverscanBottom = radeon_crtc->v_border;

sys/dev/pci/drm/radeon/atombios_crtc.c

374

args.ucOverscanTop = radeon_crtc->v_border;

sys/dev/pci/drm/radeon/atombios_crtc.c

390

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

44

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

51

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

53

switch (radeon_crtc->rmx_type) {

sys/dev/pci/drm/radeon/atombios_crtc.c

560

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

563

struct drm_encoder *encoder = radeon_crtc->encoder;

sys/dev/pci/drm/radeon/atombios_crtc.c

570

int bpc = radeon_crtc->bpc;

sys/dev/pci/drm/radeon/atombios_crtc.c

574

radeon_crtc->pll_flags = 0;

sys/dev/pci/drm/radeon/atombios_crtc.c

580

radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/

sys/dev/pci/drm/radeon/atombios_crtc.c

584

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

586

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

589

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;

sys/dev/pci/drm/radeon/atombios_crtc.c

592

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

595

&& !radeon_crtc->ss_enabled)

sys/dev/pci/drm/radeon/atombios_crtc.c

596

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

598

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

600

radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;

sys/dev/pci/drm/radeon/atombios_crtc.c

603

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

605

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

621

if (radeon_crtc->ss_enabled) {

sys/dev/pci/drm/radeon/atombios_crtc.c

622

if (radeon_crtc->ss.refdiv) {

sys/dev/pci/drm/radeon/atombios_crtc.c

623

radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

624

radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;

sys/dev/pci/drm/radeon/atombios_crtc.c

628

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

638

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;

sys/dev/pci/drm/radeon/atombios_crtc.c

640

radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;

sys/dev/pci/drm/radeon/atombios_crtc.c

643

radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

645

radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

690

if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)

sys/dev/pci/drm/radeon/atombios_crtc.c

703

if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)

sys/dev/pci/drm/radeon/atombios_crtc.c

731

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

732

radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

733

radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;

sys/dev/pci/drm/radeon/atombios_crtc.c

736

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

737

radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;

sys/dev/pci/drm/radeon/atombios_crtc.c

738

radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;

sys/dev/pci/drm/radeon/atombios_crtc.c

74

args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);

sys/dev/pci/drm/radeon/atombios_crtc.c

75

args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);

sys/dev/pci/drm/radeon/atombios_crtc.c

76

args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);

sys/dev/pci/drm/radeon/atombios_crtc.c

77

args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);

sys/dev/pci/drm/radeon/atombios_crtc.c

87

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

91

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

957

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

96

if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/atombios_crtc.c

961

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

962

int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

964

radeon_crtc->bpc = 8;

sys/dev/pci/drm/radeon/atombios_crtc.c

965

radeon_crtc->ss_enabled = false;

sys/dev/pci/drm/radeon/atombios_crtc.c

968

(radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {

sys/dev/pci/drm/radeon/atombios_crtc.c

971

radeon_get_connector_for_encoder(radeon_crtc->encoder);

sys/dev/pci/drm/radeon/atombios_crtc.c

980

radeon_crtc->bpc = radeon_get_monitor_bpc(connector);

sys/dev/pci/drm/radeon/atombios_crtc.c

988

radeon_crtc->ss_enabled =

sys/dev/pci/drm/radeon/atombios_crtc.c

989

radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,

sys/dev/pci/drm/radeon/atombios_crtc.c

994

radeon_crtc->ss_enabled =

sys/dev/pci/drm/radeon/atombios_crtc.c

996

&radeon_crtc->ss,

sys/dev/pci/drm/radeon/atombios_crtc.c

998

if (!radeon_crtc->ss_enabled)

sys/dev/pci/drm/radeon/atombios_crtc.c

999

radeon_crtc->ss_enabled =

sys/dev/pci/drm/radeon/atombios_encoders.c

1043

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/atombios_encoders.c

1044

pll_id = radeon_crtc->pll_id;

sys/dev/pci/drm/radeon/atombios_encoders.c

1531

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/atombios_encoders.c

1547

(radeon_crtc->crtc_id << 18)));

sys/dev/pci/drm/radeon/atombios_encoders.c

1549

WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));

sys/dev/pci/drm/radeon/atombios_encoders.c

1555

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_encoders.c

1850

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/atombios_encoders.c

1867

args.v1.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_encoders.c

1870

args.v1.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_encoders.c

1872

args.v1.ucCRTC = radeon_crtc->crtc_id << 2;

sys/dev/pci/drm/radeon/atombios_encoders.c

1912

args.v2.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_encoders.c

1989

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/atombios_encoders.c

1999

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/atombios_encoders.c

2020

WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_encoders.c

2023

WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_encoders.c

2026

WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_encoders.c

2029

WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_encoders.c

2032

WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/atombios_encoders.c

2035

WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/atombios_encoders.c

2051

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/atombios_encoders.c

2099

enc_idx = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_encoders.c

2134

enc_idx = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_encoders.c

457

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/atombios_encoders.c

458

bpc = radeon_crtc->bpc;

sys/dev/pci/drm/radeon/cik.c

8748

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/cik.c

8804

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/cik.c

8821

struct radeon_crtc *radeon_crtc,

sys/dev/pci/drm/radeon/cik.c

8825

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/pci/drm/radeon/cik.c

8834

if (radeon_crtc->base.enabled && mode) {

sys/dev/pci/drm/radeon/cik.c

8854

WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/cik.c

8866

if (radeon_crtc->base.enabled && mode) {

sys/dev/pci/drm/radeon/cik.c

9250

struct radeon_crtc *radeon_crtc,

sys/dev/pci/drm/radeon/cik.c

9253

struct drm_display_mode *mode = &radeon_crtc->base.mode;

sys/dev/pci/drm/radeon/cik.c

9260

if (radeon_crtc->base.enabled && num_heads && mode) {

sys/dev/pci/drm/radeon/cik.c

9286

wm_high.vsc = radeon_crtc->vsc;

sys/dev/pci/drm/radeon/cik.c

9288

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/radeon/cik.c

9326

wm_low.vsc = radeon_crtc->vsc;

sys/dev/pci/drm/radeon/cik.c

9328

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/radeon/cik.c

9348

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/pci/drm/radeon/cik.c

9352

wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/cik.c

9356

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/cik.c

9357

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/cik.c

9361

tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/cik.c

9364

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/cik.c

9365

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/cik.c

9369

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);

sys/dev/pci/drm/radeon/cik.c

9372

radeon_crtc->line_time = line_time;

sys/dev/pci/drm/radeon/cik.c

9373

radeon_crtc->wm_high = latency_watermark_a;

sys/dev/pci/drm/radeon/cik.c

9374

radeon_crtc->wm_low = latency_watermark_b;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

118

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/dce6_afmt.c

271

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/dce6_afmt.c

290

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/dce6_afmt.h

32

struct radeon_crtc;

sys/dev/pci/drm/radeon/dce6_afmt.h

48

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/dce6_afmt.h

50

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/evergreen.c

1297

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/evergreen.c

1345

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/evergreen.c

1419

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/evergreen.c

1420

struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;

sys/dev/pci/drm/radeon/evergreen.c

1423

WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/evergreen.c

1426

WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/evergreen.c

1429

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/evergreen.c

1431

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/evergreen.c

1434

RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/evergreen.c

1447

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/evergreen.c

1450

return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &

sys/dev/pci/drm/radeon/evergreen.c

1678

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/evergreen.c

1683

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/evergreen.c

1684

if (radeon_crtc->enabled) {

sys/dev/pci/drm/radeon/evergreen.c

1685

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/evergreen.c

1687

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/evergreen.c

1703

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/evergreen.c

1708

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/evergreen.c

1709

if (radeon_crtc->enabled) {

sys/dev/pci/drm/radeon/evergreen.c

1710

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/evergreen.c

1712

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/evergreen.c

1827

struct radeon_crtc *radeon_crtc,

sys/dev/pci/drm/radeon/evergreen.c

1832

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/pci/drm/radeon/evergreen.c

1854

if (radeon_crtc->base.enabled && mode) {

sys/dev/pci/drm/radeon/evergreen.c

1868

if (radeon_crtc->crtc_id % 2)

sys/dev/pci/drm/radeon/evergreen.c

1870

WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/evergreen.c

1883

if (radeon_crtc->base.enabled && mode) {

sys/dev/pci/drm/radeon/evergreen.c

2156

struct radeon_crtc *radeon_crtc,

sys/dev/pci/drm/radeon/evergreen.c

2159

struct drm_display_mode *mode = &radeon_crtc->base.mode;

sys/dev/pci/drm/radeon/evergreen.c

2168

u32 pipe_offset = radeon_crtc->crtc_id * 16;

sys/dev/pci/drm/radeon/evergreen.c

2172

if (radeon_crtc->base.enabled && num_heads && mode) {

sys/dev/pci/drm/radeon/evergreen.c

2200

wm_high.vsc = radeon_crtc->vsc;

sys/dev/pci/drm/radeon/evergreen.c

2202

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/radeon/evergreen.c

2227

wm_low.vsc = radeon_crtc->vsc;

sys/dev/pci/drm/radeon/evergreen.c

2229

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/radeon/evergreen.c

2263

c.full = dfixed_mul(c, radeon_crtc->hsc);

sys/dev/pci/drm/radeon/evergreen.c

2275

c.full = dfixed_mul(c, radeon_crtc->hsc);

sys/dev/pci/drm/radeon/evergreen.c

2283

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/pci/drm/radeon/evergreen.c

2307

WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);

sys/dev/pci/drm/radeon/evergreen.c

2308

WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);

sys/dev/pci/drm/radeon/evergreen.c

2311

radeon_crtc->line_time = line_time;

sys/dev/pci/drm/radeon/evergreen.c

2312

radeon_crtc->wm_high = latency_watermark_a;

sys/dev/pci/drm/radeon/evergreen.c

2313

radeon_crtc->wm_low = latency_watermark_b;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

230

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

273

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

77

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/evergreen_hdmi.c

78

bpc = radeon_crtc->bpc;

sys/dev/pci/drm/radeon/evergreen_hdmi.h

37

struct radeon_crtc;

sys/dev/pci/drm/radeon/evergreen_hdmi.h

60

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

62

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/r100.c

1456

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/r100.c

1499

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/r100.c

1500

crtc_id = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/r100.c

166

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/r100.c

168

struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;

sys/dev/pci/drm/radeon/r100.c

174

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/r100.c

181

WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);

sys/dev/pci/drm/radeon/r100.c

185

if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)

sys/dev/pci/drm/radeon/r100.c

193

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/r100.c

208

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/r100.c

211

return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &

sys/dev/pci/drm/radeon/r100.c

464

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/r100.c

469

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/r100.c

470

if (radeon_crtc->enabled) {

sys/dev/pci/drm/radeon/r100.c

471

if (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/r100.c

495

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/r100.c

500

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/r100.c

501

if (radeon_crtc->enabled) {

sys/dev/pci/drm/radeon/r100.c

502

if (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/r600.c

301

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/r600.c

346

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/r600.h

34

struct radeon_crtc;

sys/dev/pci/drm/radeon/r600.h

47

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/r600_cs.c

832

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/r600_cs.c

897

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/r600_cs.c

898

crtc_id = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/r600_dpm.c

158

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/r600_dpm.c

164

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/r600_dpm.c

165

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

sys/dev/pci/drm/radeon/r600_dpm.c

167

radeon_crtc->hw_mode.crtc_htotal *

sys/dev/pci/drm/radeon/r600_dpm.c

168

(radeon_crtc->hw_mode.crtc_vblank_end -

sys/dev/pci/drm/radeon/r600_dpm.c

169

radeon_crtc->hw_mode.crtc_vdisplay +

sys/dev/pci/drm/radeon/r600_dpm.c

170

(radeon_crtc->v_border * 2));

sys/dev/pci/drm/radeon/r600_dpm.c

172

vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock;

sys/dev/pci/drm/radeon/r600_dpm.c

185

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/r600_dpm.c

190

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/r600_dpm.c

191

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

sys/dev/pci/drm/radeon/r600_dpm.c

192

vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode);

sys/dev/pci/drm/radeon/r600_hdmi.c

294

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/radeon_audio.c

444

struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/radeon_audio.c

602

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/radeon_audio.c

603

bpc = radeon_crtc->bpc;

sys/dev/pci/drm/radeon/radeon_audio.h

55

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/radeon_audio.h

91

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/radeon_connectors.c

721

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_connectors.c

723

radeon_crtc->output_csc = radeon_encoder->output_csc;

sys/dev/pci/drm/radeon/radeon_cursor.c

100

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/pci/drm/radeon/radeon_cursor.c

101

WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

102

lower_32_bits(radeon_crtc->cursor_addr));

sys/dev/pci/drm/radeon/radeon_cursor.c

103

WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/radeon_cursor.c

109

if (radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/radeon_cursor.c

111

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/pci/drm/radeon/radeon_cursor.c

114

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/pci/drm/radeon/radeon_cursor.c

117

WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

118

lower_32_bits(radeon_crtc->cursor_addr));

sys/dev/pci/drm/radeon/radeon_cursor.c

119

WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/radeon_cursor.c

124

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

125

radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr);

sys/dev/pci/drm/radeon/radeon_cursor.c

127

switch (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/radeon_cursor.c

146

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_cursor.c

149

int w = radeon_crtc->cursor_width;

sys/dev/pci/drm/radeon/radeon_cursor.c

151

radeon_crtc->cursor_x = x;

sys/dev/pci/drm/radeon/radeon_cursor.c

152

radeon_crtc->cursor_y = y;

sys/dev/pci/drm/radeon/radeon_cursor.c

161

xorigin = min(-x, radeon_crtc->max_cursor_width - 1);

sys/dev/pci/drm/radeon/radeon_cursor.c

163

yorigin = min(-y, radeon_crtc->max_cursor_height - 1);

sys/dev/pci/drm/radeon/radeon_cursor.c

209

if (x <= (crtc->x - w) || y <= (crtc->y - radeon_crtc->cursor_height) ||

sys/dev/pci/drm/radeon/radeon_cursor.c

218

WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

sys/dev/pci/drm/radeon/radeon_cursor.c

219

WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/pci/drm/radeon/radeon_cursor.c

220

WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

221

((w - 1) << 16) | (radeon_crtc->cursor_height - 1));

sys/dev/pci/drm/radeon/radeon_cursor.c

223

WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

sys/dev/pci/drm/radeon/radeon_cursor.c

224

WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/pci/drm/radeon/radeon_cursor.c

225

WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

226

((w - 1) << 16) | (radeon_crtc->cursor_height - 1));

sys/dev/pci/drm/radeon/radeon_cursor.c

234

WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

238

WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

243

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

244

radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr +

sys/dev/pci/drm/radeon/radeon_cursor.c

248

if (radeon_crtc->cursor_out_of_bounds) {

sys/dev/pci/drm/radeon/radeon_cursor.c

249

radeon_crtc->cursor_out_of_bounds = false;

sys/dev/pci/drm/radeon/radeon_cursor.c

250

if (radeon_crtc->cursor_bo)

sys/dev/pci/drm/radeon/radeon_cursor.c

257

if (!radeon_crtc->cursor_out_of_bounds) {

sys/dev/pci/drm/radeon/radeon_cursor.c

259

radeon_crtc->cursor_out_of_bounds = true;

sys/dev/pci/drm/radeon/radeon_cursor.c

284

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_cursor.c

297

if ((width > radeon_crtc->max_cursor_width) ||

sys/dev/pci/drm/radeon/radeon_cursor.c

298

(height > radeon_crtc->max_cursor_height)) {

sys/dev/pci/drm/radeon/radeon_cursor.c

305

DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_cursor.c

318

&radeon_crtc->cursor_addr);

sys/dev/pci/drm/radeon/radeon_cursor.c

328

if (width != radeon_crtc->cursor_width ||

sys/dev/pci/drm/radeon/radeon_cursor.c

329

height != radeon_crtc->cursor_height ||

sys/dev/pci/drm/radeon/radeon_cursor.c

330

hot_x != radeon_crtc->cursor_hot_x ||

sys/dev/pci/drm/radeon/radeon_cursor.c

331

hot_y != radeon_crtc->cursor_hot_y) {

sys/dev/pci/drm/radeon/radeon_cursor.c

334

x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;

sys/dev/pci/drm/radeon/radeon_cursor.c

335

y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;

sys/dev/pci/drm/radeon/radeon_cursor.c

337

radeon_crtc->cursor_width = width;

sys/dev/pci/drm/radeon/radeon_cursor.c

338

radeon_crtc->cursor_height = height;

sys/dev/pci/drm/radeon/radeon_cursor.c

339

radeon_crtc->cursor_hot_x = hot_x;

sys/dev/pci/drm/radeon/radeon_cursor.c

340

radeon_crtc->cursor_hot_y = hot_y;

sys/dev/pci/drm/radeon/radeon_cursor.c

35

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_cursor.c

350

if (radeon_crtc->cursor_bo) {

sys/dev/pci/drm/radeon/radeon_cursor.c

351

struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);

sys/dev/pci/drm/radeon/radeon_cursor.c

357

drm_gem_object_put(radeon_crtc->cursor_bo);

sys/dev/pci/drm/radeon/radeon_cursor.c

360

radeon_crtc->cursor_bo = obj;

sys/dev/pci/drm/radeon/radeon_cursor.c

374

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_cursor.c

376

if (radeon_crtc->cursor_bo) {

sys/dev/pci/drm/radeon/radeon_cursor.c

379

radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x,

sys/dev/pci/drm/radeon/radeon_cursor.c

380

radeon_crtc->cursor_y);

sys/dev/pci/drm/radeon/radeon_cursor.c

39

cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/radeon_cursor.c

44

WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);

sys/dev/pci/drm/radeon/radeon_cursor.c

46

cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/radeon_cursor.c

51

WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);

sys/dev/pci/drm/radeon/radeon_cursor.c

53

cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/radeon_cursor.c

58

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);

sys/dev/pci/drm/radeon/radeon_cursor.c

64

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_cursor.c

68

WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

72

WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_cursor.c

76

switch (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/radeon_cursor.c

92

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_cursor.c

95

if (radeon_crtc->cursor_out_of_bounds)

sys/dev/pci/drm/radeon/radeon_cursor.c

99

WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_device.c

1615

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_device.c

1619

if (radeon_crtc->cursor_bo) {

sys/dev/pci/drm/radeon/radeon_device.c

1620

struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);

sys/dev/pci/drm/radeon/radeon_device.c

1738

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_device.c

1740

if (radeon_crtc->cursor_bo) {

sys/dev/pci/drm/radeon/radeon_device.c

1741

struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);

sys/dev/pci/drm/radeon/radeon_device.c

1749

&radeon_crtc->cursor_addr);

sys/dev/pci/drm/radeon/radeon_display.c

100

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

102

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/radeon/radeon_display.c

103

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/radeon/radeon_display.c

104

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/radeon/radeon_display.c

106

WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

107

WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

sys/dev/pci/drm/radeon/radeon_display.c

109

WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

114

WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

123

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_display.c

129

DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_display.c

133

WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

136

WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

138

WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

140

WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

144

WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

146

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

147

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

148

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

150

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/radeon/radeon_display.c

151

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/radeon/radeon_display.c

152

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/radeon/radeon_display.c

154

WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

155

WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

sys/dev/pci/drm/radeon/radeon_display.c

157

WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

162

WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

168

WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

1688

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_display.c

1695

radeon_crtc->h_border = 0;

sys/dev/pci/drm/radeon/radeon_display.c

1696

radeon_crtc->v_border = 0;

sys/dev/pci/drm/radeon/radeon_display.c

1707

radeon_crtc->rmx_type = RMX_OFF;

sys/dev/pci/drm/radeon/radeon_display.c

1710

radeon_crtc->rmx_type = radeon_encoder->rmx_type;

sys/dev/pci/drm/radeon/radeon_display.c

1712

radeon_crtc->rmx_type = RMX_OFF;

sys/dev/pci/drm/radeon/radeon_display.c

1714

memcpy(&radeon_crtc->native_mode,

sys/dev/pci/drm/radeon/radeon_display.c

1718

dst_v = radeon_crtc->native_mode.vdisplay;

sys/dev/pci/drm/radeon/radeon_display.c

1720

dst_h = radeon_crtc->native_mode.hdisplay;

sys/dev/pci/drm/radeon/radeon_display.c

173

WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

1730

radeon_crtc->h_border = radeon_encoder->underscan_hborder;

sys/dev/pci/drm/radeon/radeon_display.c

1732

radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;

sys/dev/pci/drm/radeon/radeon_display.c

1734

radeon_crtc->v_border = radeon_encoder->underscan_vborder;

sys/dev/pci/drm/radeon/radeon_display.c

1736

radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;

sys/dev/pci/drm/radeon/radeon_display.c

1737

radeon_crtc->rmx_type = RMX_FULL;

sys/dev/pci/drm/radeon/radeon_display.c

1739

dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);

sys/dev/pci/drm/radeon/radeon_display.c

1741

dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);

sys/dev/pci/drm/radeon/radeon_display.c

1745

if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {

sys/dev/pci/drm/radeon/radeon_display.c

1757

if (radeon_crtc->rmx_type != RMX_OFF) {

sys/dev/pci/drm/radeon/radeon_display.c

176

WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

1761

radeon_crtc->vsc.full = dfixed_div(a, b);

sys/dev/pci/drm/radeon/radeon_display.c

1764

radeon_crtc->hsc.full = dfixed_div(a, b);

sys/dev/pci/drm/radeon/radeon_display.c

1766

radeon_crtc->vsc.full = dfixed_const(1);

sys/dev/pci/drm/radeon/radeon_display.c

1767

radeon_crtc->hsc.full = dfixed_const(1);

sys/dev/pci/drm/radeon/radeon_display.c

179

WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

180

(NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |

sys/dev/pci/drm/radeon/radeon_display.c

183

WREG32(0x6940 + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

188

WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/radeon_display.c

195

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_display.c

203

if (radeon_crtc->crtc_id == 0)

sys/dev/pci/drm/radeon/radeon_display.c

250

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_display.c

253

destroy_workqueue(radeon_crtc->flip_queue);

sys/dev/pci/drm/radeon/radeon_display.c

254

kfree(radeon_crtc);

sys/dev/pci/drm/radeon/radeon_display.c

284

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/radeon_display.c

290

if (radeon_crtc == NULL)

sys/dev/pci/drm/radeon/radeon_display.c

306

if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {

sys/dev/pci/drm/radeon/radeon_display.c

309

radeon_crtc->flip_status,

sys/dev/pci/drm/radeon/radeon_display.c

365

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/radeon_display.c

370

if (radeon_crtc == NULL)

sys/dev/pci/drm/radeon/radeon_display.c

374

work = radeon_crtc->flip_work;

sys/dev/pci/drm/radeon/radeon_display.c

375

if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {

sys/dev/pci/drm/radeon/radeon_display.c

378

radeon_crtc->flip_status,

sys/dev/pci/drm/radeon/radeon_display.c

385

radeon_crtc->flip_status = RADEON_FLIP_NONE;

sys/dev/pci/drm/radeon/radeon_display.c

386

radeon_crtc->flip_work = NULL;

sys/dev/pci/drm/radeon/radeon_display.c

390

drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);

sys/dev/pci/drm/radeon/radeon_display.c

394

drm_crtc_vblank_put(&radeon_crtc->base);

sys/dev/pci/drm/radeon/radeon_display.c

396

queue_work(radeon_crtc->flip_queue, &work->unpin_work);

sys/dev/pci/drm/radeon/radeon_display.c

412

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];

sys/dev/pci/drm/radeon/radeon_display.c

414

struct drm_crtc *crtc = &radeon_crtc->base;

sys/dev/pci/drm/radeon/radeon_display.c

453

while (radeon_crtc->enabled &&

sys/dev/pci/drm/radeon/radeon_display.c

468

radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_display.c

471

radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);

sys/dev/pci/drm/radeon/radeon_display.c

473

radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;

sys/dev/pci/drm/radeon/radeon_display.c

487

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_display.c

504

work->crtc_id = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/radeon_display.c

51

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_display.c

548

base -= radeon_crtc->legacy_display_base_addr;

sys/dev/pci/drm/radeon/radeon_display.c

57

DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_display.c

58

WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

588

if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {

sys/dev/pci/drm/radeon/radeon_display.c

594

radeon_crtc->flip_status = RADEON_FLIP_PENDING;

sys/dev/pci/drm/radeon/radeon_display.c

595

radeon_crtc->flip_work = work;

sys/dev/pci/drm/radeon/radeon_display.c

60

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

602

queue_work(radeon_crtc->flip_queue, &work->flip_work);

sys/dev/pci/drm/radeon/radeon_display.c

61

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

62

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

64

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/radeon/radeon_display.c

65

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/radeon/radeon_display.c

66

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/radeon/radeon_display.c

68

WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_display.c

684

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/radeon_display.c

686

radeon_crtc = kzalloc(sizeof(*radeon_crtc), GFP_KERNEL);

sys/dev/pci/drm/radeon/radeon_display.c

687

if (radeon_crtc == NULL)

sys/dev/pci/drm/radeon/radeon_display.c

690

radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);

sys/dev/pci/drm/radeon/radeon_display.c

691

if (!radeon_crtc->flip_queue) {

sys/dev/pci/drm/radeon/radeon_display.c

692

kfree(radeon_crtc);

sys/dev/pci/drm/radeon/radeon_display.c

696

drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);

sys/dev/pci/drm/radeon/radeon_display.c

698

drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);

sys/dev/pci/drm/radeon/radeon_display.c

699

radeon_crtc->crtc_id = index;

sys/dev/pci/drm/radeon/radeon_display.c

700

rdev->mode_info.crtcs[index] = radeon_crtc;

sys/dev/pci/drm/radeon/radeon_display.c

703

radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;

sys/dev/pci/drm/radeon/radeon_display.c

704

radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;

sys/dev/pci/drm/radeon/radeon_display.c

706

radeon_crtc->max_cursor_width = CURSOR_WIDTH;

sys/dev/pci/drm/radeon/radeon_display.c

707

radeon_crtc->max_cursor_height = CURSOR_HEIGHT;

sys/dev/pci/drm/radeon/radeon_display.c

709

dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;

sys/dev/pci/drm/radeon/radeon_display.c

710

dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;

sys/dev/pci/drm/radeon/radeon_display.c

713

radeon_atombios_init_crtc(dev, radeon_crtc);

sys/dev/pci/drm/radeon/radeon_display.c

715

radeon_legacy_init_crtc(dev, radeon_crtc);

sys/dev/pci/drm/radeon/radeon_display.c

84

WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);

sys/dev/pci/drm/radeon/radeon_display.c

89

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_display.c

95

DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_display.c

96

WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

98

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_display.c

99

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_kms.c

276

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_kms.c

277

*value = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1040

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1047

if (radeon_crtc->crtc_id == 0) {

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1050

if (radeon_crtc->rmx_type != RMX_OFF) {

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1120

struct radeon_crtc *radeon_crtc)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1122

if (radeon_crtc->crtc_id == 1)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1123

radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1124

drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

129

switch (radeon_crtc->rmx_type) {

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

299

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

305

if (radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

327

radeon_crtc->enabled = true;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

330

if (radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

337

if (dev->num_crtcs > radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

344

if (dev->num_crtcs > radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

346

if (radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

353

radeon_crtc->enabled = false;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

379

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

42

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

44

WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

45

WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

46

WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

471

radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

473

base -= radeon_crtc->legacy_display_base_addr;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

533

if (radeon_crtc->crtc_id == 1)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

54

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

546

WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

549

if (radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

554

WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

555

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

556

WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

577

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

596

DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

650

if (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

66

struct drm_display_mode *native_mode = &radeon_crtc->native_mode;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

725

WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

726

WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

727

WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

728

WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

737

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

773

if (radeon_crtc->crtc_id)

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

853

if (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1003

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1005

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1151

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1228

if (radeon_crtc->crtc_id == 0) {

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1255

if (radeon_crtc->crtc_id == 0) {

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1293

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1295

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1540

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1541

if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

192

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

230

if (radeon_crtc->crtc_id == 0) {

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

251

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

253

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

583

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

589

if (radeon_crtc->crtc_id == 0) {

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

629

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

631

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

780

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

847

if (radeon_crtc->crtc_id == 0) {

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

869

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

871

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

945

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

983

if (radeon_crtc->crtc_id == 0) {

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

241

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

246

radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

247

if (radeon_crtc->crtc_id == 1)

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

532

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

549

radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

595

if (radeon_crtc->crtc_id == 1)

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

598

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/radeon/radeon_mode.h

249

struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];

sys/dev/pci/drm/radeon/radeon_mode.h

50

#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)

sys/dev/pci/drm/radeon/radeon_mode.h

902

struct radeon_crtc *radeon_crtc);

sys/dev/pci/drm/radeon/radeon_mode.h

904

struct radeon_crtc *radeon_crtc);

sys/dev/pci/drm/radeon/radeon_mode.h

919

void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);

sys/dev/pci/drm/radeon/radeon_pm.c

1718

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/radeon_pm.c

1730

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_pm.c

1731

if (radeon_crtc->enabled) {

sys/dev/pci/drm/radeon/radeon_pm.c

1732

rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_pm.c

1791

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/radeon_pm.c

1806

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/radeon_pm.c

1808

rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);

sys/dev/pci/drm/radeon/radeon_pm.c

1810

if (!radeon_crtc->connector)

sys/dev/pci/drm/radeon/radeon_pm.c

1813

radeon_connector = to_radeon_connector(radeon_crtc->connector);

sys/dev/pci/drm/radeon/rs600.c

121

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/rs600.c

122

struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;

sys/dev/pci/drm/radeon/rs600.c

123

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/rs600.c

128

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/rs600.c

131

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/rs600.c

134

WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/rs600.c

137

WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/rs600.c

139

WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/rs600.c

144

if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)

sys/dev/pci/drm/radeon/rs600.c

152

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/rs600.c

157

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/rs600.c

160

return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &

sys/dev/pci/drm/radeon/rs600.c

326

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/rs600.c

331

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/rs600.c

332

if (radeon_crtc->enabled) {

sys/dev/pci/drm/radeon/rs600.c

333

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/rs600.c

335

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/rs600.c

344

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/rs600.c

349

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/rs600.c

350

if (radeon_crtc->enabled) {

sys/dev/pci/drm/radeon/rs600.c

351

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/rs600.c

353

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/rs690.c

273

struct radeon_crtc *crtc,

sys/dev/pci/drm/radeon/rs780_dpm.c

54

struct radeon_crtc *radeon_crtc;

sys/dev/pci/drm/radeon/rs780_dpm.c

64

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/pci/drm/radeon/rs780_dpm.c

65

pi->crtc_id = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/rv515.c

680

void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)

sys/dev/pci/drm/radeon/rv515.c

924

struct radeon_crtc *crtc,

sys/dev/pci/drm/radeon/rv770.c

802

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/rv770.c

803

struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;

sys/dev/pci/drm/radeon/rv770.c

804

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/rv770.c

809

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/rv770.c

812

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/rv770.c

815

WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/rv770.c

818

if (radeon_crtc->crtc_id) {

sys/dev/pci/drm/radeon/rv770.c

825

WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/rv770.c

827

WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/rv770.c

832

if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)

sys/dev/pci/drm/radeon/rv770.c

840

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/rv770.c

845

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/radeon/rv770.c

848

return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &

sys/dev/pci/drm/radeon/si.c

1948

struct radeon_crtc *radeon_crtc,

sys/dev/pci/drm/radeon/si.c

1953

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/pci/drm/radeon/si.c

1967

if (radeon_crtc->base.enabled && mode) {

sys/dev/pci/drm/radeon/si.c

1980

WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/si.c

1992

if (radeon_crtc->base.enabled && mode) {

sys/dev/pci/drm/radeon/si.c

2275

struct radeon_crtc *radeon_crtc,

sys/dev/pci/drm/radeon/si.c

2278

struct drm_display_mode *mode = &radeon_crtc->base.mode;

sys/dev/pci/drm/radeon/si.c

2290

if (radeon_crtc->base.enabled && num_heads && mode) {

sys/dev/pci/drm/radeon/si.c

2322

wm_high.vsc = radeon_crtc->vsc;

sys/dev/pci/drm/radeon/si.c

2324

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/radeon/si.c

2349

wm_low.vsc = radeon_crtc->vsc;

sys/dev/pci/drm/radeon/si.c

2351

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/radeon/si.c

2387

c.full = dfixed_mul(c, radeon_crtc->hsc);

sys/dev/pci/drm/radeon/si.c

2399

c.full = dfixed_mul(c, radeon_crtc->hsc);

sys/dev/pci/drm/radeon/si.c

2407

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/pci/drm/radeon/si.c

2411

arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/si.c

2415

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/si.c

2416

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/si.c

2420

tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/si.c

2423

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/si.c

2424

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/pci/drm/radeon/si.c

2428

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);

sys/dev/pci/drm/radeon/si.c

2431

WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);

sys/dev/pci/drm/radeon/si.c

2432

WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);

sys/dev/pci/drm/radeon/si.c

2435

radeon_crtc->line_time = line_time;

sys/dev/pci/drm/radeon/si.c

2436

radeon_crtc->wm_high = latency_watermark_a;

sys/dev/pci/drm/radeon/si.c

2437

radeon_crtc->wm_low = latency_watermark_b;

sys/dev/pci/drm/radeon/si_dpm.c

5262

struct radeon_crtc *radeon_crtc = NULL;

sys/dev/pci/drm/radeon/si_dpm.c

5270

radeon_crtc = rdev->mode_info.crtcs[i];

sys/dev/pci/drm/radeon/si_dpm.c

5275

if (radeon_crtc == NULL)

sys/dev/pci/drm/radeon/si_dpm.c

5278

if (radeon_crtc->line_time <= 0)

sys/dev/pci/drm/radeon/si_dpm.c

5283

radeon_crtc->crtc_id) != PPSMC_Result_OK)

sys/dev/pci/drm/radeon/si_dpm.c

5288

radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)

sys/dev/pci/drm/radeon/si_dpm.c

5293

radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)