qwz_pcic_write32
qwz_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
qwz_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
qwz_pcic_write32(sc, WLAON_WARM_SW_ENTRY, 0);
qwz_pcic_write32(sc, offset, (v & ~mask) | value);
qwz_pcic_write32(sc, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
qwz_pcic_write32(sc, GCC_GCC_PCIE_HOT_RST, val);
qwz_pcic_write32(sc, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
qwz_pcic_write32(sc, WLAON_QFPROM_PWR_CTRL_REG, val);
qwz_pcic_write32(sc, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
qwz_pcic_write32(sc, MHI_CTRL, MHI_CTRL_RESET_MASK);
qwz_pcic_write32(sc, PCIE_TXVECDB, 0);
qwz_pcic_write32(sc, PCIE_TXVECSTATUS, 0);
qwz_pcic_write32(sc, PCIE_RXVECDB, 0);
qwz_pcic_write32(sc, PCIE_RXVECSTATUS, 0);
void qwz_pcic_write32(struct qwz_softc *, uint32_t, uint32_t);
sc->ops.write32 = qwz_pcic_write32;