qwz_pci_read
val = qwz_pci_read(sc, offset);
(void) qwz_pci_read(sc, ATH12K_PCI_WINDOW_REG_ADDRESS);
val = qwz_pci_read(sc,
val = qwz_pci_read(sc, window_start +
val = qwz_pci_read(sc, window_start +
psc->bhi_off = qwz_pci_read(sc, MHI_BHI_OFFSET);
psc->bhie_off = qwz_pci_read(sc, MHI_BHIE_OFFSET);
ee = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
state = qwz_pci_read(sc, MHI_STATUS);
state = qwz_pci_read(sc, MHI_STATUS);
ee = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
psc->bhi_off = qwz_pci_read(sc, MHI_BHI_OFFSET);
reg = qwz_pci_read(sc, MHI_CTRL);
reg = qwz_pci_read(sc, MHI_STATUS);
reg = qwz_pci_read(sc, MHI_CTRL);
reg = qwz_pci_read(sc, MHI_CHDBOFF);
reg = qwz_pci_read(sc, MHI_ERDBOFF);
reg = qwz_pci_read(sc, MHI_CFG);
reg = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
reg = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
reg = qwz_pci_read(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS);
reg = qwz_pci_read(sc,
reg = qwz_pci_read(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS);
reg = qwz_pci_read(sc,
psc->bhi_off = qwz_pci_read(sc, MHI_BHI_OFFSET);
ee = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
state = qwz_pci_read(sc, MHI_STATUS);
uint32_t qwz_pci_read(struct qwz_softc *, uint32_t);